Synopsys and TSMC to accelerate 2nm innovation for advanced SoC designs

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Synopsys has announced that its digital and custom/analogue design flows are now certified for TSMC's N2 process technology, enabling faster delivery of advanced-node SoCs with higher quality.

Both flows are said to be seeing strong momentum, with the digital design flow achieving multiple tape-outs and the analogue design flow adopted for several design starts.

The design flows, powered by the full-stack AI-driven EDA suite, have been able to deliver a significant lift in productivity. Synopsys Foundation and Interface IP in development for the TSMC N2 process will help reduce integration risk and speed time to market for advanced HPC, AI, and mobile SoCs.

In addition, Synopsys AI-driven design technologies, including Synopsys, are able to optimise N2 design to improve the power, performance, and area.

"The Synopsys digital and analogue design flows for the TSMC N2 process represent a significant investment by Synopsys across the full EDA stack, helping designers jumpstart their N2 designs, differentiate their SoCs with increasingly better power, performance, and chip density, and accelerate their time to market," said Sanjay Bali, vice president of Strategy and Product Management for the EDA Group at Synopsys. "Our close collaboration with TSMC through every generation of TSMC's process technologies enables us to deliver unmatched EDA and IP solutions that customers need to innovate and strengthen their competitive advantage."

The Synopsys analogue flow enables efficient reuse of designs from node to node on TSMC advanced processes. As part of the certified EDA flows, Synopsys provides interoperable process design kits (iPDKs) and Synopsys IC Validator physical verification for full-chip physical signoff.

The certified EDA flows are available now.