Synopsys and Samsung Foundry accelerate multi-die system design

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Synopsys and Samsung Foundry are deepening their collaboration to help chipmakers accelerate the design of 2.5D and 3D multi-die systems on Samsung's most advanced process technologies.

The collaboration addresses key requirements of multi-die systems for intense computing applications including high-performance computing, AI, automotive and mobile.

Providing a combination of certified EDA reference flows including Synopsys 3DIC Compiler and UCIe IP for die-to-die connectivity, customers will be able to accelerate the development of multi-die systems on Samsung Foundry's 5nm, 4nm and 3nm processes and using I-Cube and X-Cube technologies.

"Semiconductor designers are dealing with new levels of complexity as they develop high-performance systems for data-intensive applications on the most advanced geometries," said Sanjay Bali, vice president of Strategy and Product Management for the EDA Group at Synopsys. "The strong collaboration between Synopsys and Samsung on the development of UCIe IP and certified EDA flows addresses emerging requirements for multi-die systems utilising Samsung's advanced process nodes and multi-die integration flow."

By integrating multiple dies on different nodes into a single package, using die-to-die interconnects such as UCIe and advanced fan-out wafer-level packaging, designers can meet their stringent performance and time-to-market requirements for compute-intensive designs.

In addition, the Synopsys Multi-Die Solution supports Samsung Foundries' I-Cube and X-Cube technologies, a family of 2.5 and 3D silicon stacking and advanced packaging technologies. The flexibility of multi-die systems provides an efficient way to deliver task-optimised applications.

"Compute-intensive workloads for our data-driven world require customers to meet ambitious power, performance and area targets for even the most demanding process technologies," said Sangyun Kim, vice president of Foundry Design Technology Team at Samsung Electronics. "Together, we’re optimising multi-die designs, from early to full system implementation and signoff analysis to IP readiness."

Synopsys 3DIC Compiler supports Samsung's new 3D CODE standard and is part of the broader Synopsys Digital Design Family and, combined with Synopsys Fusion Compiler and AI-driven design enabled by suite of technologies, enables unified system-on-chip (SoC) to multi-die system co-optimisation.

Ansys Redhawk-SC Electrothermal multi-physics technology is integrated with Synopsys 3DIC Compiler to address the power and thermal signoff for multi-die systems.

Synopsys digital design technology are available now for Samsung Foundry's advanced process technologies.

Synopsys UCIe IP on Samsung SF5/4/3 is in development.