Synopsys accelerates chip innovation on TSMC’s advanced processes

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Synopsys has announced significant EDA and IP collaborations with TSMC for advanced node designs.

Credit: Synopsys

Among the newest collaborations that have been announced is a co-optimised Photonic IC flow, which looks to address the application of silicon photonics technology in terms of better power, performance, and transistor density.

Synopsys is also working with TSMC on digital and analogue design flows which are production-ready for TSMC’s N3/N3P and N2 process technologies. The two companies are collaborating on next-generation AI-driven flows, including Synopsys, for design productivity and optimisation.

In addition, Synopsys is developing a broad portfolio of Foundation and Interface IP on TSMC N2/N2P and, together with Keysight and Ansys, has introduced a new integrated radio frequency (RF) design migration flow from TSMC’s N16 process to its N6RF+ technology.

“The advancements in Synopsys’ production-ready EDA flows and photonics integration with our 3DIC Compiler, which supports the 3Dblox standard, combined with a broad IP portfolio enable Synopsys and TSMC to help designers achieve the next level of innovation for their chip designs on TSMC’s advanced processes,” said Sanjay Bali, vice president of strategy and product management for the EDA Group at Synopsys.

“Our close collaboration with Open Innovation Platform (OIP) ecosystem partners like Synopsys has enabled customers to address the most challenging design requirements, all at the leading edge of innovation from angstrom-scale devices to complex multi-die systems across a range of high-performance computing designs,” explained Dan Kochpatcharin, head of Design Infrastructure Management Division at TSMC. “Together, we will help engineering teams create the next generation of differentiated designs on TSMC’s most advanced process nodes with faster time to results.”

Synopsys’ production-ready digital and analogue design flows for TSMC N3P and N2 process technologies have been deployed across a range of AI, high-performance computing, and mobile designs, enabling rapid migration from one process node to another. A new flow is available for TSMC N5 to N3E migration, adding to Synopsys’ established flows for TSMC N4P to N3E and N3E to N2 processes.

In addition, interoperable process design kits (iPDKs) and Synopsys IC Validator physical verification runsets are available for design teams to efficiently transition designs to TSMC advanced process technologies.

Synopsys IC Validator enables full-chip physical signoff to handle the increasing complexity of physical verification rules and is now certified on TSMC N2 and N3P process technologies.

The high volume of data processing for AI training requires low-latency, power-efficient, and high-bandwidth interconnects, driving the adoption of optical transceivers and near-/co-packaged optics using silicon photonics technology. Synopsys and TSMC are developing end-to-end multi-die electronic and photonic flow solutions for TSMC’s Compact Universal Photonic Engine (COUPE) technology to enhance system performance and function. This flow spans photonic IC design with Synopsys OptoCompiler and integration with electrical ICs utilising Synopsys 3DIC Compiler and Ansys multiphysics analysis technologies.

Synopsys is developing a broad portfolio of Foundation and Interface IP for the TSMC N2 and N2P process technologies to enable faster silicon success for complex AI, high-performance computing, and mobile SoCs.

High-quality PHY IP on N2 and N2P, including UCIe, HBM4/3e, 3DIO, PCIe 7.x/6.x, MIPI C/D-PHY and M-PHY, USB, DDR5 MR-DIMM, and LPDDR6/5x, allows designers to benefit from the PPA improvements of TSMC’s most advanced process nodes.

In addition, Synopsys is providing a silicon-proven Foundation and Interface IP portfolio for TSMC N3P, including 224G Ethernet, UCIe, MIPI C/D-PHY and M-PHY, USB/DisplayPort and eUSB2, LPDDR5x, DDR5, and PCIe 6.x, with DDR5 MR-DIMM in development.