Production-proven digital and custom design flows have achieved certification on the TSMC N3E process and, in addition, the flows and Synopsys' broad Foundation and Interface IP portfolio have achieved numerous tapeouts on the TSMC N3E process.
The collaborative efforts on the advanced process technology also extend to analogue design migration, AI-driven designs and physical verification scaling in the cloud.
"TSMC's and Synopsys' long history of collaboration to advance semiconductor innovation addresses the increasingly complex challenges of emerging applications," said Dan Kochpatcharin, Head of Design Infrastructure Management Division at TSMC. "Synopsys' latest achievements in EDA and IP on the TSMC N3E process technology provide our mutual customers with robust solutions that help them meet the stringent power, performance and area targets for their innovative designs."
"These recent achievements mark another significant milestone of the continuous, successful collaboration between Synopsys and TSMC," added Sanjay Bali, vice president of Marketing and Strategy for the EDA Group at Synopsys. "Our substantial investment in providing certified EDA solutions and a silicon-proven IP portfolio for TSMC's most advanced processes gives designers a low-risk path to achieving their critical design requirements."
TSMC's N3E process extends its 3nm family with enhanced power, performance and yield, meeting the demands of workload-intensive applications like high-performance computing, AI and mobile. A joint effort on AI-driven design enablement with Synopsys DSO.ai technology and Synopsys Fusion Compiler has resulted in multiple validated N3E test cases with better PPA and faster design closure.
Aside from the IP readiness and certified flows, Synopsys is working closely with TSMC to scale physical verification in the cloud, using the Synopsys IC Validator product for N3E on the Synopsys Cloud software-as-a-service offering.
This work highlights how access to unlimited CPU capacity in the cloud delivers faster physical verification iterations and both companies are also now enabling customers to seamlessly transition existing designs on earlier process nodes to the TSMC N3E process.
