The company’s NuLink PHY and NuGear technologies address the critical need for a commercially viable approach to enabling high performance and cost-effectiveness in the connection of homogeneous and heterogenous architectures on a standard, organic chip substrate. It has proven to achieve similar bandwidth, power efficiency, and latency as die-to-die implementations using advanced packaging technologies, but without the other drawbacks of some other specialised approaches.
Eliyan’s chiplet packaging method has been designed to meet the scale of performance and integration required in a broad range of compute intensive applications for data centres, cloud computing, AI and graphics.
The company’s founding CEO Ramin Farjadrad is the inventor of the Bunch of Wires (BoW) scheme, which has been adopted by the Open Compute Project (OCP) and its NuLink technology is backward compatible with Universal Chiplet Interconnect Express (UCIe), a standard developed by Intel and donated to the UCIe Consortium.
Eliyan’s Series A round, which was led by Tracker Capital Management, will enable fast-track design, testing, and implementation ramp-up, culminating with the demonstration of the commercial readiness of Eliyan’s chiplet interconnect technology in a tapeout using TSMC’s 5nm process.
The design confirms Eliyan’s ability to achieve twice the bandwidth at less than half the power consumption of current interconnect methods and does so using a standard system-in-package (SIP) manufacturing and packaging process. The ability to implement chiplet-based systems in organic packages will enable the creation of larger and higher performance solutions at considerably lower power and cost of materials.
The company’s first silicon is expected in the first quarter of 2023.
Commenting Eliyan CEO and co-founder, Ramin Farjadrad, said, “Our approach supports and is compliant with the overall industry move toward chiplet-optimised interconnect protocols, including the UCIe standard as well as High Bandwidth Memory (HBM) protocols. This financial investment by industry leaders and the successful implementation of our design in 5nm validates our strategy and prepares us for broader commercialisation efforts.”
Eliyan’s approach to connecting multi-die chip architectures is achieved without the need for complex and advanced packaging solutions such as silicon interposers. This is essential to cost-effectively leveraging the potential of the fast-growing chiplet-based architectures that experts agree are the pathway to extend Moore’s Law.
