This is a cutting-edge innovation that’s aimed at improving high-performance packaging solutions for artificial intelligence (AI) and data centre markets in addition supporting Intel’s 18A process node.
As the demands of AI and data centre workloads continue to grow in complexity, reliable communication between chiplets and 3DICs is crucial - high-speed data transfer and efficient power delivery are essential to meet the performance demands of next-generation semiconductor applications.
The semiconductor industry is looking to address these challenges through emerging open standards, such as Universal Chiplet Interconnect Express (UCIe) and Bunch of Wires (BoW). These standards define interconnect protocols for chiplets and 3DICs within advanced 2.5D/3D or laminate/organic packages, enabling consistent, high-quality integration across different design platforms.
By adopting these standards and verifying chiplets for compliance and link margin, Keysight EDA and Intel Foundry are helping to grow the chiplet interoperability ecosystem. Their collaboration aims to reduce development costs, mitigate risk, and accelerate innovation in semiconductor design.
Keysight EDA’s Chiplet PHY Designer, the latest solution for high-speed digital chiplet design tailored to AI and data centre applications, now offers advanced simulation capabilities for the UCIe 2.0 standard and introduces support for the Open Computer Project BoW standard. As an advanced, system-level chiplet design and die-to-die (D2D) design solution, Chiplet PHY Designer enables pre-silicon level validation, streamlining the path to tapeout.
Commenting Suk Lee, VP & GM of Ecosystem Technology Office, Intel Foundry, said, “Our collaboration with Keysight EDA on EMIB-T silicon bridge technology is a pivotal step in advancing high-performance packaging solutions. By integrating standards like UCIe 2.0, we enhance chiplet design flexibility for AI and data centre applications, accelerating innovation and ensuring our customers meet next-generation demands with precision.”
"Keysight EDA's pioneering Chiplet PHY Designer continues to redefine pre-silicon validation, empowering chiplet designers with rapid, accurate verification,” said Niels Faché, Vice President and General Manager, Keysight’s Design Engineering Software. He continued, “By proactively embracing evolving standards like UCIe 2.0 and BoW, and now with critical support for Intel Foundry’s EMIB-T, we're enabling engineers to accelerate innovation and eliminate costly design iterations before manufacturing."
