Synopsys and Samsung Foundry collaborate to enable 3nm process technology

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In a move designed to drive the adoption of Samsung's 3nm gate-all-around (GAA) technology for designs requiring optimal power, performance and area (PPA) it has, in collaboration with Synopsys, produced multiple test chip tape-outs.

Based on Synopsys digital and custom design tools and flows and certified for Samsung Foundry's most advanced process, customers using Samsung Foundry's SF3 technology will benefit from the approximately 50% reduced power, 30% improved performance and 30% smaller area that the technology node has demonstrated versus Samsung’s existing SF5E process.

"Today's demanding mobile, high-performance computing and AI applications require power and performance levels that stretch the limits of small geometries," said Sangyun Kim, corporate vice president of the Foundry Design Technology Team at Samsung Electronics. "Our longstanding collaboration with Synopsys on EDA design flow certifications provides mutual customers with substantial power, performance and area advantages."

Samsung Foundry streamlined its 3nm process development costs and timeline, efficiently evaluating its process options based on PPA design metrics. The foundry continues to include Synopsys DSO.ai technology in its flow, utilising the machine learning capabilities to massively scale the exploration of choices in chip design workflows and expedite development of its process.

"Synopsys' strategic collaboration with Samsung Foundry has enabled us to remain in lockstep through every generation of their process technology advancements," said Shankar Krishnamoorthy, GM of the EDA Group at Synopsys. "By providing leading EDA design flows certified on the most advanced Samsung 3nm technology, our mutual customers can maximize the capabilities of their advanced SoC designs and achieve a faster path to silicon success."