It has been optimised to provide maximum designer productivity for designers of advanced 5G, HPC, AI and IoT applications using the Samsung 3nm GAA process technology.
Complexity at advanced nodes means designers are looking for new methods to shorten design cycles. Through close collaboration, Samsung and Synopsys have been able to provide a flow that is optimised to overcome design complexity and provide the best possible productivity for 3nm GAA design.
Key features of the flow include in-design electromigration analysis, which shortens design closure time by providing accurate electromigration analysis before the layout is complete. It also includes Live design rule checking (DRC) with Synopsys' IC Validator physical verification solution, enabling layout engineers to quickly check for design rule violations directly from the layout canvas as they work.
The AMS reference flow provides a proven methodology for designing at 3nm GAA process technology. This methodology, which has been validated by Samsung, includes a full set of documented flows and design examples. Covered topics include design entry, circuit simulation, Monte Carlo analysis, noise analysis, RF analysis, aging and EM/IR analysis, parasitic simulation, layout and signoff.
"With the Synopsys AMS Reference flow, designers can quickly deploy 3nm GAA technology for their most demanding applications, such as artificial intelligence, 5G networking, automotive, the Internet of Things and advanced data centres," said Sangyun Kim, VP of Foundry Design Technology Team at Samsung Electronics. "The advanced methodologies enabled by Synopsys help our customers and internal IP developers to create analogue and mixed-signal designs more efficiently."