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Synopsys accelerates high-performance computing SoC designs

1 min read

Synopsys has announced the industry's broadest portfolio of high-quality IP on TSMC's 5nm process technology for high-performance computing system-on chips (SoCs).

The company's DesignWare IP portfolio on the TSMC process, encompassing interface IP for the most widely used high-speed protocols and foundation IP, will help to accelerate the development of SoCs for high-end cloud computing, AI accelerators, networking and storage applications.

The combination of Synopsys' DesignWare IP and TSMC's 5nm process is intended to enable designers to achieve the more aggressive performance, power, and density requirements of their designs, while lowering integration risk.

"Our long-term collaboration with Synopsys has resulted in delivering DesignWare IP on the most advanced TSMC processes, enabling our mutual customers to achieve many first-pass silicon successes in a wide range of markets including high-performance computing," said Suk Lee, senior director of the Design Infrastructure Management Division at TSMC. "Synopsys' broad DesignWare IP portfolio on TSMC's process technologies helps designers quickly incorporate the necessary functionality into their designs, while benefiting from the significant power and performance boost of our 5nm process technology, the most advanced foundry solution."

"For nearly two decades, Synopsys has been at the forefront of delivering high-quality DesignWare IP with unmatched power, performance, and area for every generation of TSMC's process technologies," said John Koeter, senior vice president of marketing and strategy for IP at Synopsys. "By providing the industry's broadest interface and foundation IP portfolio on TSMC's 5nm process, Synopsys is helping our mutual customers speed development for a new era of high-performance computing SoCs."

The DesignWare Interface and Foundation IP for TSMC's 5nm process technology targeting high-performance computing SoCs are scheduled to be available in late Q2 of 2020.