OPENEDGES completes 7nm HBM3 memory subsystem test chip tape-out

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OPENEDGES Technology has announced the successful completion of the first tape-out of an advanced 7nm process technology test chip for its HBM3 memory subsystem IP, including the PHY and memory controller.

The update provides in-depth insights into the tape-out that represents the completion of the design phase, the beginning of silicon characterization and validation, and the expansion pathway to more silicon-proven IPs supporting the latest JEDEC DRAM standards.

The OPENEDGES 7nm HBM3 memory subsystem IP test chip was designed in compliance with the JEDEC JESD238 HBM3 standard, delivering up to 8.4Gbps data rates per IO in a 2.5D integration platform. The HBM3 PHY IP has the capability to support up to 16 independent and asynchronous channels, each with 2x32-bit DWORD pseudo-channels.

Additional features include multiple frequency set points (FSPs), DBI, ECC, SEV, and Parity (data and command/address parity), as well as lane repair, also known as Interconnect Redundancy Remapping, which detects, repairs, and remaps repairable interconnect issues automatically, making them transparent to the memory controller.

In addition, it’s equipped with a proprietary microcontroller for firmware-based training and a firmware-based API to work with DRAM’s IEEE 1500 for training and testing.

Optimised traffic monitoring with power-down and self-refresh states helps to improve power efficiency, and the out-of-order scheduling algorithm, combined with the highly optimised pipeline architecture, provides an efficient solution for applications requiring high memory bandwidth, particularly in the fields of artificial intelligence (AI), machine learning (ML), and general-purpose graphics processing units (GPGPU).

“As HBM3 can process vast amounts of data quickly, it is becoming more essential and recognised as an advanced technology that is necessary for the faster processing of big data,” said Sean Lee, the CEO of OPENEDGES Technology. “Taking advantage of OPENEDGES’ past success with various tape-outs, we will continue collaborating with our client to silicon-prove the HBM3 7nm memory subsystem IP and introduce it to the market”.

By incorporating an architecturally optimised approach to analogue mixed-signal design and partitioning across its PHY IP portfolio, OPENEDGES is able to ensure integration is straightforward for its hard-IP components and enables the latest DDR standards even on older technology nodes.

The PHY IPs offered by OPENEDGES support JEDEC-compliant standards, such as HBM3, GDDR6, and LPDDR5X/5/4X/4, in multiple foundries and technology nodes.