The Six Semiconductor announces tape-out of two 7nm test chips

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The Six Semiconductor (TSS), a subsidiary of OPENEDGES Technology and supplier of cutting-edge high-speed memory PHYs, has successfully taped out two memory sub-system validation test chips at the same time in a 7nm process.

TSS has worked in close collaboration with imec.IC-link US, part of imec, the R&D and innovation hub located in Leuven, Belgium and the first test chip taped out was TSS’s LPDDR5X/5/4X/4 PHY IP validation vehicle, supporting the JESD209-5B LPDDR5X DDR standard up to 8533Mbps.

LPDDR5X is currently the fastest LPDDR DRAM standard with a speed extension above the 6400Mbps data rate that LPDDR5 has to offer.

The LPDDR5X PHY is capable of operating with backward compatibility to LPDDR4 mode, providing flexibility when it comes to product DRAM selection requirements. Complete with OPENEDGES’ DDR controller (OMC), which is equipped with advanced features in power management, and a generation 2 PHY architecture, the LPDDR5X PHY (OPHY) looks to address the low-power DDR memory subsystem market.

The second validation vehicle taped out was the HBM3 PHY test chip, which was designed to operate up to 8.4Gbps in a 2.5D integration platform. The HBM3 test platform is completed with the HBM3 OMC  and HBM3 OPHY on the same test die, and the HBM3 die stack is integrated together in a 2.5D assembly.

In the process of implementing this 2.5D system, Imec.IC-link worked with TSS on the evaluation, design, optimisation, and all the logistics.

As opposed to traditional DRAM, the HBM3 memory subsystem requires the entire SoC, silicon interposer, and package substrate to be designed concurrently, which requires meticulous planning and know-how at the full system level.

Commenting Yiyi Wang, Head of imec.IC-link US, said, “Delivering the GDSII from Netlist hand-off in only a few months was not trivial. And the effort spent on an advanced 2.5D integration manufacturing proven flows was significant. 2.5D SoC integration requires a highly complex co-design phase, including chip backend layout design, interposer design, substrate design, and BGA package design.”

"The successful tape-out of these two advanced memory subsystem validation test chips is a testament to the exceptional work of our team and our partnership with imec.IC-link US. They were instrumental in providing the technical know-how and support required to bring these cutting-edge technologies to fruition. Their expertise in ASIC solutions enabled us to achieve our goals in a timely manner and with the highest level of quality. We are grateful for their support and collaboration on these projects and look forward to working with them again in the future," said Sean Lee, CEO of OPENEDGES Technology.