Marvell unveils 3nm data infrastructure IP portfolio

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Marvell Technology has announced a 3nm silicon technology platform that will support its work across cloud data centre, carrier, enterprise, and automotive markets.

Leveraging the company’s on-going work in 5nm, which includes the industry's first 5nm Data Processing Unit (DPU) – the OCTEON 10 platform, a suite of advanced technologies, will enable cutting-edge monolithic and multi-die solutions in the most advanced process node and will provide customers with a combination of performance, power, and density (size) necessary to meet demanding infrastructure requirements whether for compute, next generation 100T Ethernet switching and 5G Advanced baseband processing.

The 3nm Marvell silicon, which is now in fabrication with TSMC on its 3nm shuttle, is available for new product designs and includes foundational IP building blocks such as long reach SerDes, PCIe Gen6 PHY, and several standards-based die-to-die interconnect technologies for managing data flow across the data infrastructure.

This 3nm development follows numerous 5nm solutions from Marvell – in production or development – that spans a broad portfolio of electro-optics, switch, PHY, compute, 5G baseband, and storage products, as well as a wide range of custom ASIC programmes.

Additionally, this IP portfolio is compatible with 2.5D packaging technologies such as TSMC's 2.5D Chip-on-Wafer-on-Substrate (CoWoS) and will enable Marvell to develop some of the most advanced multi-die, multi-chiplet systems-in-package (SiP) for its infrastructure products and co-development of custom ASIC solutions optimised for some of the most challenging infrastructure use cases, such as machine learning.

With data and internet traffic approximately doubling every two years, cloud service providers, software-as-a-service (SaaS) companies, and telecommunication carriers are increasingly relying on silicon that has been optimised by semiconductor providers to deliver breakthrough performance and bandwidth while minimising power consumption, emissions, and cost.

Achieving these objectives, particularly for hyperscale cloud providers, requires silicon partners to move quickly to the most advanced process node available to take advantage of the inherent scaling benefits in power, performance, and density.

By developing and validating each of the critical IP blocks in silicon early in the availability of the 3nm process, Marvell said that it will be able to significantly accelerate customers' time-to-market while reducing the design risk and verification efforts associated with its complex monolithic or multi-die SoC designs.

"Marvell teamed with TSMC to provide our customers with the power to build high-performance, cloud-optimised solutions for the most demanding applications requiring the industry's first 3nm IP on silicon," said Raghib Hussain, President of Products & Technologies at Marvell. "The 3nm platform provides advantages for a wide range of solutions, from standard and application-specific SoCs to highly custom chips with unique and innovative designs."