Broadcom debuts 5nm ASIC for data centre and Cloud infrastructure

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Broadcom has announced the sampling of its 5nm ASIC device for data centre and cloud infrastructure.

Built on TSMC’s N5 process and measuring 625 mm2, this device incorporates PCIe Gen5 protocol, 112-Gbps SerDes, HBM2e memory operating at 3.6 Gbps, and 3.6-Tbps Die2Die PHY IP utilising TSMC CoWoS interposer technology.

In addition, Broadcom has multiple ASIC devices in development targeting artificial intelligence (AI), high performance computing (HPC) and 5G wireless infrastructure applications.

Among the 5nm technology portfolio highlights are:

  • High speed multi-protocol 112-Gbps, 64-Gbps and 32-Gbps SerDes cores
  • HBM2e and HBM3 protocol solution
  • High bandwidth Die2Die PHY for multi-die SoC and silicon disaggregation
  • High performance and high-density standard cell libraries and memory compilers
  • Advanced packaging solutions including multi-chip-modules and 2.5D stacking.

“Broadcom’s pioneering ASIC leverages both N5, the industry’s most advanced silicon technology, and our high-performance CoWoS integration solution to address the demanding requirements of next-generation cloud and data centre applications,” said Dr. Kevin Zhang, senior vice president of business development at TSMC. “We’re excited to see the new applications Broadcom’s ASIC platform will enable, and look forward to continued partnership to empower end customers and their innovations.”

“This first-to-market 5nm ASIC extends Broadcom’s embedded SoC leadership and paves the way for new innovations across AI, HPC, 5G and hyperscale infrastructure applications,” said Frank Ostojic, senior vice president and general manager of the ASIC Product Division at Broadcom. “Our innovative IP, proven design methodology and partnership with TSMC continue to provide leadership solutions with power, performance and time to market advantage for our customers.”