This solution is part of Marvell’s IP portfolio for custom AI compute platforms and enables multi-chip accelerator designs up to 2.8x larger than conventional single-die implementations.
This approach will enable more efficient die-to-die interconnect, lower power consumption, increased chiplet yields, as well as lower product cost, according to Marvell and provides a manufacturing alternative to traditional interposer-based multi-chip approaches.
The packaging platform has been qualified with a major hyperscaler and is now ramping in production.
Chip packaging has become critical for increasing AI compute density while effectively managing power, thermal dissipation, optical I/O, signal integrity, and other factors that impact the performance and reliability in multi-die chiplet designs. Simultaneously, there are challenges associated with rising supply chain complexity and extended lead times when it comes to scaling advanced packaging solutions.
According to Marvell, its packaging solution will enable hyperscalers to overcome many of these barriers, accelerating time-to-market while offering greater supply chain flexibility.
This is the latest innovation in a series of advancements Marvell has introduced for its custom XPU solutions which are a highly optimised multi-chip packaging platform that’s been designed from the ground up with Marvell’s custom HBM and CPO solutions in mind. Taken together, Marvell is working to build a broad technology platform to enable improved custom XPU design.
"Advanced packaging is one of the primary vehicles for advancing compute density in AI clusters and cloud," said Will Chu, senior vice president and general manager of Custom Cloud Solutions at Marvell. "Without it, AI infrastructure would be significantly more expensive and power-hungry.”
"Chiplets constitute one of the most dynamic segments of the semiconductor market. We anticipate that chiplet processor revenue will grow by 31% per year to reach $145 billion by 2030," said James Sanders, senior analyst at TechInsights. "Advanced packaging technologies are critical to the evolution of chiplets, giving designers a framework in which to experiment."
Interposers serve as the foundational layer with compute, dies, memory, and other components stacked above and communicating through the interposer.
The Marvell re-distribution layer (RDL) offers an alternative to traditional silicon interposers for data centre applications – it integrates 1390 mm2 of silicon and four pieces of high-bandwidth memory 3/3E (HBM3/3E) memory stacks and utilises six interposer RDL layers which enables multi-die AI accelerator solutions that are 2.8 times larger than the largest possible single-chip design.
The Marvell multi-die packaging solution allows for shorter die-to-die interconnects and a modular RDL interposer.
The interposer reduces design cost through its modular design, according to Marvell.
In conventional chiplets, a single interposer will span the floor space of the chips it connects well as any area between them. If two computing cores are on opposite sides of a chiplet package, the interposer will cover the entire space.
By contrast, Marvell RDL interposers are form-fitted to individual computing dies and connected by high-bandwidth paths. This approach reduces the need for materials and also increases chiplet yields by enabling manufacturers to replace individual dies.
The Marvell multi-die packaging platform enables the integration of passive devices to reduce potential signal noise within the chiplet package caused by the power supply. In collaboration with the packaging ecosystem, Marvell has extended the solution to support multiple components within a single package, enabling the integration of the most complex AI designs.
In addition, hyperscalers can now employ the packaging technology to build XPUs with HBM3 and HBM3E memory and Marvell said that it was actively qualifying the technology for future HBM4 designs.
