Keysight introduces Chiplet PHY Designer

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Keysight Technologies has announced the Chiplet PHY Designer, the latest member in its family of high-speed digital design and simulation tools that provides die-to-die (D2D) interconnect simulation.

This is a key step in verifying performance for heterogeneous and 3D integrated circuit (IC) designs commonly referred to as chiplets.

The new electronic design automation (EDA) tool is the industry’s first to provide in-depth modelling and simulation capabilities that enable chiplet designers to accurately verify that their designs meet specifications of the Universal Chiplet Interconnect Express (UCIe) standard.

UCIe is emerging as a leading chiplet interconnect specification in the semiconductor industry. It is an open standard that defines the interconnect between chiplets within an advanced 2.5D or 3D package.

UCIe is currently in process of being supported or adopted by many of the top semiconductor equipment and EDA tool vendors as well as foundries and chiplet designers. Designers who are using the interconnect standard are helping establish a broad ecosystem for chiplet interoperability and commerce.

Keysight EDA’s research and development team has been working on modelling and simulating high-speed digital interfaces aligned with industry specifications over a number of years. For example, the ADS Memory Designer offers comprehensive memory interface coverage such as GDDR7, DDR5, LPDDR5, and HBM3 with its IBIS-AMI modeler.

Key features of the Chiplet PHY Designer physical-layer simulator include:

Supports UCIe physical layer standard – automated parsing of signals following the standard naming conventions, automated connections between multiple dies through package interconnects, standard driven simulation setup such as speed grade, and intuitive measurement setup through specialised probe component.

Measurement of voltage transfer function (VTF) – precisely computes a VTF to ensure UCIe specification compliance and analyses system bit error rate (BER) down to 1e-27 or 1e-32 levels. Measures eye diagram height, eye width, skew, mask margin, and BER contour.

Analysis of forwarded clocking to accurately capture the asynchronous clocking behaviour.

According to Adrien Auge, Senior Staff Applications Engineer, Alphawave Semi, the ability to validate chiplet solutions ensures seamless operation and interoperability for 2.5D/3D solutions.

“Chiplet PHY Designer simplifies the electrical simulation process for large die-die electrical connectivity, such as UCIe. It provides engineers and designers a quick and easy path to extract electrical compliance of their solutions against the latest revision of the specification. Furthermore, by complying with the latest IBIS modelling specification for electrical I/O, physical integrators can delve deeper into the chiplet electrical validation process, leveraging our detailed models to obtain pre-silicon performance predictions.”

Niels Faché, Vice President and General Manager, Keysight EDA, said, “Interconnect modelling is critical to system design and performance. Chiplet PHY Designer accelerates validation of chiplet subsystems, from one D2D PHY through interconnect channels to another D2D PHY, much earlier in the design cycle. It enables 3D IC designers to solve critical interconnect performance problems improving predictive virtual prototyping to speed time-to-market.”