Cadence launches Verisium AI-driven Verification Platform

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Cadence Design Systems has unveiled the Cadence Verisium Artificial Intelligence (AI)-Driven Verification Platform.

This suite of applications leverages big data and AI to optimise verification workloads, boost coverage and accelerate root cause analysis of bugs and has been built on the new Cadence Joint Enterprise Data and AI (JedAI) Platform and is natively integrated with the Cadence verification engines.

As SoC complexity continues to increase, verification has become more important in terms of system time to market, often consuming significantly more compute and human resources than any other silicon engineering task. The release of the Verisium platform represents, according to Cadence, a generational shift from single-run, single-engine algorithms in electronic design automation (EDA) to algorithms that leverage big data and AI to optimise multiple runs of multiple engines across an entire SoC design and verification campaign.

By deploying the Verisium platform, all verification data, including waveforms, coverage, reports and log files, are brought together in the Cadence JedAI Platform. Machine learning (ML) models are built, and other proprietary metrics are mined from this data making it possible to create a new class of tools that will dramatically improve verification productivity.

 Using the JedAI Platform, Cadence is able to unify its computational software innovations in data and AI across Verisium AI-driven verification to Cadence Cerebrus Intelligent Chip Explorer’s AI-driven implementation and Optimality Intelligent System Explorer’s AI-driven system analysis.

The initial suite of apps available in the Verisium platform are:

  • Verisium AutoTriage: Builds ML models that help automate the repetitive task of regression failure triage by predicting and classifying test failures with common root causes.
  • Verisium SemanticDiff: Provides an algorithmic solution to compare multiple source code revisions of an IP or SoC, classify these revisions and rank which updates are most disruptive to the system's behavior to help pinpoint potential bug hotspots.
  • Verisium WaveMiner: Applies powerful AI engines to analyse waveforms from multiple runs and determine which signals, at which times, are most likely to represent the root cause of a test failure.
  • Verisium PinDown: Integrates with the Cadence JedAI Platform and industry-standard revision control systems to build ML models of source code changes, test reports and log files to predict which source code check-ins are most likely to have introduced failures.
  • Verisium Debug: Delivers a holistic debug solution from IP to SoC and from single run to multi-run, offering fast and comprehensive interactive and post-process debug flows with waveform, schematic, driver tracing and SmartLog technologies. Verisium Debug is natively integrated with the Cadence JedAI Platform and other Verisium apps to enable AI-driven root cause analysis with the support of simultaneous automatic comparison of passing and failing tests.
  • Verisium Manager: Brings Cadence’s full flow IP and SoC-level verification management solution with verification planning, job scheduling, and multi-engine coverage natively onto the Cadence JedAI Platform and extends it to support AI-driven test suite optimisation to improve compute farm efficiency.

Verisium Manager also integrates directly with other Verisium apps, enabling interactive push-button deployment of the complete Verisium platform from a unified browser-based management console.

“AI and big data are transforming the world around us,” said Paul Cunningham, senior vice president and general manager of the System & Verification Group at Cadence. “To realise this transformation in our core EDA business, we must build new technologies that optimise across multiple runs and engines. With the Verisium platform, we enter a new era of AI-driven verification built on the Cadence JedAI Platform. Users are already seeing dramatic improvements in their verification productivity and efficiency using the Verisium platform.”

Commenting on the new platform S. Brian Choi, Corporate VP, Samsung Electronics, said, “As SoC complexity continues to grow, SoC-level verification has become a rate-limiting step in our tape out schedules. We see a great opportunity to leverage AI and big data to dramatically improve design and verification productivity. We are working closely with Cadence to deploy the Verisium platform on our mobile SoC designs and are already seeing impressive results to automatically triage and root cause bugs.”