The aim, according to Siemens, is to significantly improve the Integrated Circuit (IC) verification process and make engineering teams more productive.
Questa One delivers faster engines and requires fewer workloads to support complex designs from IP to System-on-a-chip (SoC) to Systems, and was developed with advanced 3D-ICs, chiplet-based designs and software-defined architectures in mind.
“Questa One transforms the IC design process to address the verification productivity gap and solves the challenges associated with increasingly complex designs,” said Abhi Kolpekwar, VP & GM, Digital Verification Technologies, Siemens Digital Industries Software.
“Questa One uses new technical advances to deliver the fastest functional, fault and formal verification engines available. However, customers tell us that performance alone isn’t enough - they also need deeper connectivity across verification, validation and test workflows, which Questa One now provides. Combined with our application of AI, Siemens’ verification solutions are yielding step-function gains in productivity by early adopters across smart creation, smart regression, smart analysis, smart engine and smart debug domains.”
Siemens has worked with a number of leading companies to develop the Questa One which delivers a connected, data-driven, scalable solution that breaks the Verification Productivity Gap 2.0 bottleneck, caused by the increasing complexity of technologies such as 3D-ICs, chiplet-based designs and software-defined architectures.
Those challenges have been further compounded by a critical talent shortage, and growing demands for enhanced security, lower power consumption, reliability and sustainability.
The Questa One smart verification solution encompasses multiple technical breakthroughs including:
Questa One Coverage Acceleration software has achieved coverage goals 50x faster than traditional testbench solvers combining higher/faster coverage results with the benefits of Universal Verification Methodology (UVM) constrained random test generation.
Questa One DFT Simulation Acceleration software has achieved 8x faster gate-level design for test (DFT) serial pattern simulations leveraging Questa One Parallel Simulation software and is tightly integrated with the Tessent Streaming Scan Network (SSN) architecture.
Questa One Fault Simulation Acceleration software has delivered 48x faster performance and supports both functional safety and DFT fault simulation applications. It supports the User Defined Fault Modelling (UDFM) capability in Tessent.
Questa One Stimulus Free Verification software empowers engineers to achieve new levels of productivity. By combining engines and unifying applications it has been able to reduce overall processing times from over 24 hours to under 1 minute on complex open source SoC level reference designs.
The integration of 20 different stimulus-free analyses, AI and automation deliver new solutions such as linting with auto-correction and generative AI SVA property creation and verification.
Questa One Avery Verification IP software is based on Avery’s high-quality VIP and high-coverage Compliance Test Suites (CTS). Protocol-aware debug and protocol-aware coverage analytics help increase productivity, and accelerated VIP enables the same CTS, testbench and stimulus on Questa One Sim to be re-used on Veloce CS emulation and prototyping systems.
