The platform enables a move from single-run, single-engine algorithms in electronic design automation (EDA) to algorithms that leverage big data and artificial intelligence (AI) to optimise multiple runs of multiple engines across an entire SoC design and verification flow.
Engineers will be able to use the JedAI Platform to extract actionable intelligence from massive volumes of chip design and verification data and, in the process, open the door to a new generation of AI-driven design and verification tools that will significantly improve productivity and power, performance and area (PPA).
According to Cadence, the platform unifies big data analytics across its AI platforms, Verisium verification, Cadence Cerebrus implementation, and Optimality system optimisation, as well as third-party silicon lifecycle management systems.
With the new platform, engineers can now manage both structured and unstructured data, including:
- Design data such as waveforms and coverage in functional verification, physical layout shapes, timing/power/voltage/variation analysis reports, design RTL, netlist and SDC specifications in design implementation
- Workload data such as runtime, memory usage and disk space usage, as well as metadata about the inputs to each job and dependencies between them
- Workflow data such as the tools and methodology used to create a design
The JedAI Platform makes it easier to manage design complexities associated with emerging consumer, hyperscale computing, 5G communications, automotive and mobile applications, and more.
Customers using Cadence analogue/digital/PCB implementation, verification, and analysis software, and even third-party applications, can use the platform to unify and analyse all their big data analytics. Furthermore, the platform is cloud-enabled, offering highly scalable compute resources in a secure design environment from top cloud providers.
“To enable the semiconductor industry to continue on its strong growth trajectory, it’s critical that the chip design process becomes much more efficient to keep pace with market demands,” said Pat Moorhead, CEO, founder and chief analyst at Moor Insights & Strategy. “Improving design processes through AI and big data analytics creates a clear benefit for engineering teams who can now extract key learnings from the vast quantities of EDA data right at their fingertips.”
Customers using the Cadence JedAI Platform have access to the following benefits:
Highly scalable: Enterprise-grade scalability and security, enabling design optimization across multiple runs, tools, users, designs, and EDA domains
Actionable intelligence: Quickly compares metrics across different versions of the same design and/or multiple designs, providing recommended actions to improve PPA and increase verification coverage
Workflow management technology: Integrated workflow management capability allows users to efficiently capture chip design methodologies and automatically transfer design data between projects through data connectors
Customised analytics: Offers open industry-standard user interfaces such as Python, Jupyter Notebook and REST APIs, enabling designers to create custom analytics applications
“As chip design size and complexity has increased exponentially over the past decade, the volume of design and verification data has also increased with it,” said Dr. Venkat Thanvantri, VP of AI R&D at Cadence. “Previously, we saw that once a chip design project was completed, the valuable data was deleted to make way for the next project. There are valuable learnings in the legacy data, and the Cadence JedAI Platform makes it easy for engineering teams to access these learnings and apply them to future designs to deliver optimal engineering productivity and PPA and ultimately more predictable, higher quality product outcomes.”