Cadence and Arm to accelerate data centre design using Neoverse V2 platform

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Cadence Design Systems has announced an expanded collaboration with Arm to speed up data centre silicon development using the Arm Neoverse V2 platform.

Cadence has fine-tuned its AI-driven RTL-to-GDS digital flow for Neoverse V2 and delivered corresponding 5nm and 3nm Rapid Adoption Kits (RAKs), allowing customers to achieve power, performance and area (PPA) targets faster. In addition, the Cadence AI-driven verification full flow supports Neoverse V2, providing designers with optimal verification throughput and preparedness for Arm SystemReady compliance.

The Cadence RTL-to-GDS digital full flow RAKs for 3nm and 5nm nodes includes the Genus Synthesis Solution, Modus DFT Software Solution, Innovus Implementation System, Quantus Extraction Solution, Tempus Timing Solution and ECO Option, Voltus IC Power Integrity Solution, Conformal Equivalence Checking, Conformal Low Power and the AI-based Cadence Cerebrus Intelligent Chip Explorer.

The digital RAKs provide Arm Neoverse V2 designers with several key benefits. For example, the Cadence Cerebrus AI capabilities automate and scale digital chip design, delivering better PPA and improves designer productivity. Cadence iSpatial technology provides an integrated and predictable implementation flow for the faster design closure. The RAKs also include a smart hierarchy flow that delivers optimal turnaround times on large, high-performance CPUs. The Tempus ECO technology offers signoff-accurate final design closure based on path-based analysis. Finally, the RAKs incorporate the GigaOpt activity-aware power optimisation engine to significantly reduce dynamic power consumption.

The Cadence AI-driven verification full flow also includes the Xcelium Logic Simulation Platform, Palladium Enterprise Emulation Platforms, Protium Enterprise Prototyping Systems, Helium Virtual and Hybrid Studio, Jasper Formal Verification Platform, Verisium Manager Planning and Coverage Closure tools, Perspec System Verifier, and VIP and System VIP tools and content for Arm-based designs.

The Cadence verification full flow provides Neoverse V2 designers with pre-silicon server base system architecture (SBSA) compliance verification and optimised PCI Express (PCIe) integration.

In addition, the Cadence Helium Virtual and Hybrid Studio includes editable virtual and hybrid platform reference designs for Neoverse V2, incorporating Arm Fast Models to jumpstart early software development and verification. The Helium gearshift technology enables customers to position workloads in a high-performance hybrid environment before shifting to a fully accurate RTL environment, offering detailed verification using either the Palladium or Protium platforms.

“The growing demand for complex workloads such as big data analytics, HPC and ML inference requires specialised compute solutions that achieve greater performance and efficiency,” said Eddie Ramirez, vice president of go-to-market, Infrastructure Line of Business at Arm. “Through this latest collaboration, customers can leverage Cadence’s comprehensive digital and verification flows to validate their solutions and bring the power of their Neoverse V2-based products to market faster. Furthermore, silicon partners will get the benefits of these advanced design flows when running their EDA workloads on Arm-enabled servers and cloud instances."

According to Kam Kittrell, vice president, product management in the Digital & Signoff Group at Cadence, “Through our expanded collaboration with Arm, customers using the AI-driven digital full flow 3nm and 5nm RAKs for Neoverse V2 designs benefit from improved productivity and faster time to tape-out. In addition, by optimising our AI-driven verification full flow, customers have access to all the tools necessary to verify RTL and perform pre-silicon software validation to ensure full system success.”