Built on RISC-V the device combines CPU, vector, and tensor capabilities in a single, unified all-in-one architecture, enabling zero-latency AI compute across applications from edge AI to datacentre-scale LLMs.
Said to be able to deliver up to 256 TOPS (Tera Operations Per Second) at 2GHz, Cervell scales from C8 to C64 configurations, allowing designers to tune performance to application needs - from 8 TOPS INT8 at 1GHz in compact edge deployments to 256 TOPS INT4 in high-end AI inference.
Commenting Roger Espasa, CEO of Semidynamics, said, “Cervell is designed for a new era of AI compute. As an NPU, it delivers the scalable performance needed for everything from edge inference to large language models. It’s fully programmable, with no lock-in thanks to the open RISC-V ISA, and deeply customisable down to the instruction level. Combined with our Gazillion Misses memory subsystem, Cervell removes traditional data bottlenecks and gives chip designers a powerful foundation to build differentiated, high-performance AI solutions.”
NPUs are purpose-designed to accelerate the types of operations AI relies on, enabling faster insights, lower latency, and greater energy efficiency and Cervell NPUs have been purpose-built to accelerate matrix-heavy operations, enabling higher throughput, lower power consumption, and real-time response.
By integrating NPU capabilities with standard CPU and vector processing in a unified architecture, designers can eliminate latency and maximise performance across diverse AI tasks, from recommendation systems to deep learning pipelines.
Cervell is tightly integrated with Gazillion Misses, Semidynamics’ memory management subsystem delivering:
- Up to 128 simultaneous memory requests, eliminating latency stalls
- Over 60 bytes/cycle of sustained data streaming
- Massively parallel access to off-chip memory, essential for large model inference and sparse data processing
Consequently, this NPU architecture can maintain full pipeline saturation, even in bandwidth-heavy applications like recommendation systems and deep learning.
Cervell is fully customisable, and customers can:
- Add scalar or vector instructions
- Configure scratchpad memories and custom I/O FIFOs
- Define memory interfaces and synchronization schemes
- Request bespoke features to suit your application
As demand grows for differentiated AI hardware, chip designers are increasingly looking for ways to embed proprietary features directly into their processor cores. While many IP providers offer limited configurability from fixed option sets, Semidynamics has taken a different approach, enabling deep customisation at the RTL level, including the insertion of customer-defined instructions.
This allows companies to integrate their unique “secret sauce” directly into the solution protecting their ASIC investment from imitation and ensuring the design is fully optimised for power, performance, and area.
With a flexible development model that includes early FPGA drops and parallel verification, Semidynamics is able to help customers accelerate time-to-market while reducing project risk.
