Delivering 'open core surgery'

5 mins read

Neil Tyler talks to the CEO and founder of Semidynamics and looks at the core architecture they have developed for the RISC-V community.

Founded in Barcelona in 2016, Semidynamics is a European supplier of high-bandwidth high-performance cores with vector units targeted at machine learning and artificial intelligence applications.

The company’s founder and CEO is Roger Espasa, spoke with New Electronics after attending the RISC-V Summit held in Barcelona, earlier this year.

Espasa started his career, having gained a Phd in Computer Science from Universitat Politècnica de Catalunya in 1997, with the Alpha Microprocessor Group on a vector extension to the Alpha architecture.

The Alpha team was ultimately acquired by Intel and Espasa then found himself working for them until 2014. In that time, he led a team developing a vector extension for the x86 ISA which was initially deployed in the Larrabee and Knight's Corner product and which then became the AVX-512 extension.

He also led the team implementing the texture sampling unit for the original Larrabee chip and worked on the core for the Knight's Landing product (14nm) and led the core development for the follow-on Knights Hill 10nm product.

In 2014, Espasa joined Broadcom but when the project he was working on was scrapped he decided to form his own business and Semidynamics came into being.

“Our first contract was with Esperanto Technologies for whom we developed a 7nm architecture for machine learning. We also helped design the Avispado RISC-V core, which was targeted at high-bandwidth applications and supported an open vector interface to vector processing units,” Espasa explains.

A business reset

“However, I realised that working for one customer was not ideal and operating in effect as a provider of design services was not going to be scalable. So, as a company we decide to develop our own IP.”

Semidynamics received funding from the European Union and got considerable support from the Barcelona Supercomputing Centre.

“Developing and growing a team was not a new experience for me, I’d done it at both Intel and Broadcom, but that’s not to say it doesn’t come without its challenges.

“Today there are 45 people here at Semidynamics but it hasn’t been easy to get the skilled people that we’ve needed, despite more tech companies coming to Spain. We’ve seen competition for talent increase significantly.”

According to Espasa Spain has three main technology centres. One being Barcelona and the others in Malaga and Valencia.

“Cisco, for example, recently announced that it was opening a facility in Barcelona and that does make it harder to attract talent because as a small business we can’t compete in terms of salaries. What we can offer though, is the opportunity to work at the cutting edge. We’re developing CPUs, RISC-V vector units and engineers can immerse themselves in the challenges associated with artificial intelligence and machine learning.

“Obviously I’d like to have seen the business develop faster but we are attracting new customers and there’s a lot of interest in our work,” said Espasa. He continued, “It’s taken six years to get where we are today, but I would say that we are well into our second phase. 2019 and our decision to create our own IP was certainly a major reset for the business and I was probably overly optimistic as to where we would be today. For anybody starting a business it takes time to successful deliver a new technology, especially new IP, and there is then the added pressure of finding buyers who will need a good reason to buy from you. 

“It’s all about relationship building with customers and building confidence in what you have to offer, but we’ve got there.”

Having attended the RISC-V Summit in Barcelona, Espasa was obviously pleased at the reaction among the developers, architects, technical decision and policy makers who were attending the event when they got to see the company’s IP in action.

“RISC-V is set to account for 14 per cent of the chip market by 2025 and there has been a surge in announcements around the technology. Many companies are developing product lines based on RISC-V and with our heritage in high performance and vector units it was an obvious space for us to enter,” he explains.

According to Espasa traditional RISC-V processor cores have had configurations that were fixed by the vendor or had a very limited number of configurable options such as cache size, address bus size, interfaces and a few other control parameters.

“By contrast our IP cores are designed to enable the customer to have total control over the configuration, whether that’s in terms of new instructions, separate address spaces, new memory accessing capabilities, and so forth. As a result, we can precisely tailor a core to meet each project’s needs so there are no unrequired overheads or compromises.”

He makes the point that Semidynamics’ IP makes it possible to implement a customer’s ‘secret sauce’ features into the RTL in a matter of weeks, which he claims to be, “something that no-one else offers.”

“Every designer using RISC-V wants to have the perfect set of Power, Performance and Area along with unique differentiating features and now, for the first time, they can have just that from us,” explained Espasa.

New customisable IP and cores

Over the past few month Semidynamics has accelerated the roll-out of new technology and has recently announced an entirely customisable Vector Unit to go with its range of fully customisable 64-bit RISC-V cores.

The Vector Unit is compliant with the RISC-V Vector Specification 1.0 and with its customisable features offers enhanced data handling capabilities.

“We also recently announced our Atrevido core which is unique in that we can do ‘Open Core Surgery’ on it which means we can actually open up the core and change the inner workings to add features or special instructions to create what is effectively a totally bespoke solution that meets the specific need of the customer.

“We have taken the same approach with our new Vector Unit in order to rapidly process massive amounts of data, which is critical when it comes to AI and machine learning.”  

A Vector Unit is composed of several 'vector cores', roughly equivalent to a GPU core, that perform multiple calculations in parallel. Semidynamics' vector core can be tailored to support different data types depending on the customer’s target application domain.

Semidynamics has equipped its Vector Unit with a high-performance, cross-vector-core network that provides all-to-all connectivity between the vector cores at high bandwidth, even for the very large, 32-vector core option. The unit is used for specific instructions in the RISC-V standard that shuffle data between the different vector cores.

“This means that the Vector Unit can process unprecedented amounts of data bits,” explained Espasa. “And to fetch all this data from memory, we have our Gazzillion technology that can handle up to 128 simultaneous requests for data and track them back to the correct place in whatever order they are returned.”

According to Espasa, “These innovative technologies will take RISC-V to a whole new level with the fastest handling of big data currently available that will open up opportunities in many application areas.”

The company continues to innovate and last month launched the next member of its Atrevido family of 64-bit cores. The Atrevido 423 has a wider, 4-way pipeline, allowing for the decoding and retirement of up to two times more instructions than its recently launched, 2-way, 223 core. “It is coupled with more functional units, which significantly increases the IPC (instructions-per-cycle),” explained Espasa.

Having left stealth mode, the company is starting to have a real impact in the fast-growing RISC-V community.

“We have successfully created the core architecture that the RISC-V community really wants – one that is fully customisable. No-one else has such a complex RISC-V core that can be totally configured to perfectly meet the specific needs of each project rather than having to use an off-the-shelf core and compromise.”