Infineon introduces 650 V CoolMOS CFD7A for fast electric vehicle charging

Infineon Technologies has expanded its 650 V CoolMOS CFD7A portfolio with the introduction of the QDPAK package.

This package family is designed to provide equivalent thermal capabilities with improved electrical performance over the well-known TO247 THD devices, enabling more efficient energy utilisation in onboard chargers and DC-DC converters.

Efficient and powerful electric vehicle charging systems help reduce charging times and vehicle weight, increasing design flexibility and reduce the total cost of ownership of the vehicle. This new addition complements the existing CoolMOS CFD7A series, offering versatility with top-side and bottom-side cooled packages. The QDPAK TSC (top side cooled), enables designers to achieve higher power densities and optimal PCB space utilisation.

The 650 V CoolMOS CFD7A offers several features for reliable operation in high-voltage applications. Thanks to its reduced parasitic source inductance, the device can minimise electromagnetic interference (EMI), ensuring clear signals and consistent performance. The Kelvin source pin also provides improved precision for current sensing, ensuring accurate measurements even in challenging conditions.

With a creepage distance suitable for high voltage applications, as well as high current capability and high-power dissipation (P tot) of up to 694 W at 25°C, it is a versatile and powerful device for a wide range of high-voltage applications.

New system designs using 650 V CoolMOS CFD7A in QDPAK TSC will maximise PCB space use, doubling power density and enhancing thermal management via substrate thermal decoupling. This approach simplifies assembly, eliminates board stacking and reduces the need for connectors, thereby lowering system costs. The power switch reduces thermal resistance by up to 35 percent, providing high power dissipation that outperforms standard cooling solutions.

This feature overcomes the thermal limitations of bottom side cooled SMD designs using FR4 PCBs, resulting in a significant boost in system performance. The optimised power loop design locates drivers near the power switch, improving reliability by reducing stray inductance and chip temperatures. Overall, these features contribute to a cost-effective, robust, and efficient system ideal for modern power needs.

The QDPAK TSC package has been registered as a JEDEC standard for high-power applications, helping to establish a broad adoption of TSC in new designs with one standard package design and footprint.