Cadence announces DRAM verification solution

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Cadence Design Systems has developed a DRAM verification solution, that will allow customers to test and optimise system-on-chip (SoC) designs for data centre, consumer, mobile and automotive applications.

Using the verification solution, which delivers up to 10X increased verification throughput, customers will be able to quickly and effectively perform IP-to-SoC-level verification of advanced designs with multiple DDR interfaces.

Modern SoC designs leverage advanced memory technologies, such as LPDDR5x, DDR5, HBM3 and GDDR6, which require rigorous verification at the PHY and IP levels to ensure compliance with the JEDEC standard as well as SoC-level verification to meet application-specific system performance definitions and data and cache coherency requirements.

“DRAM memory verification requires unique methods to ensure that all timing, power and throughput requirements are met in various conditions,” said Paul Cunningham, senior vice president and general manager, R&D, in the System & Verification Group at Cadence. “With the industry’s first full DRAM verification solution, we’re enabling our customers to verify their IP designs effectively and ensure their designs comply with the JEDEC standard specification as well as the memory subsystem application-specific performance metrics to provide the fastest path to IP and system verification closure.”

The new DRAM verification solution enables IP-level verification through Cadence PHY VIPs and memory models with a direct and seamless path to SoC-level verification. The Cadence System VIP solution, including the System Performance Analyzer, System Traffic Libraries and System Scoreboard, all with built-in integration and content for DRAM interfaces, enable faster and more efficient memory subsystem and SoC verification for simulation and emulation environments.

The solution also includes Cadence TripleCheck technology, which provides users with a verification plan linked to a specification, including JEDEC, DFI and PHY, comprehensive coverage models, and a test suite to ensure compliance with the interface specification.