This collaboration looks to equip SoC design teams with automotive-grade RISC-V IPs and the appropriate tools for early firmware and MCAL (Microcontroller Abstraction Layer) development.
The toolset released as part of the collaboration provides the capabilities for multi-core, multi-hart, verification, debugging, performance tuning, timing, and coverage analysis. The toolset can be used with Andes RISC-V development boards and MachineWare high-performance virtual prototyping solutions. Moreover, TASKING iSYSTEM debug adapters will be available to support Andes RISC-V processors to enable the connection with the toolset.
Andes Technology, a provider of 32/64-bit RISC-V processor cores, introduced the first ISO 26262 fully compliant RISC-V processor IP – the N25F-SE - in 2022 with ASIL-B certification. Andes is also gearing up to unveil the ASIL-B certified D25F-SE that’s equipped with a RISC-V P-extension (SIMD/DSP) ISA draft for efficient manipulation of multiple data in a single instruction in the fourth quarter of 2023.
In addition, Andes is working to deliver mission-critical ASIL-D certified cores based on their popular CPU IPs.
The goal of this partnership is to offer comprehensive support for functional safety solution development, particularly in the realm of firmware and MCAL development. These resources will subsequently be employed by their customers within the automotive supply chain.
MachineWare’s ultra-fast virtual prototypes facilitate simulation of complex hardware/software systems for software analysis, verification and development as well as architecture exploration. With SIM-V MachineWare offers a high-speed RISC-V simulator that can be integrated in a full-system simulation, or Virtual Platform (VP) to simulate entire SoCs or ECUs.
Besides pre-silicon availability, VPs offer many advantages over physical prototypes, as they enable for deep, non-intrusive introspection and are extremely scalable either on-premise or in the cloud.
The combination of these products will enable users to easily switch between virtual and physical SoCs, applying the same tools and automation scripts without any changes to the users’ process. This allows software developers to start the development process before silicon is available and identify and fix potential bugs and security issues at an early stage, shortening time-to-market.
According to Gerard Vink, responsible for RISC-V at TASKING, “This partnership offers an integrated solution needed to drive the adoption of RISC-V based SoCs in the automotive domain. The certified IPs and tools reduce the efforts of all parties in the supply chain to comply with functional safety and cybersecurity requirements, enabling them to focus on innovation and product differentiation.”