Semi-damascene with high-aspect-ratio processing reduces path to line resistance by half

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imec has presented, at this year’s IEEE International Interconnect Technology Conference, a number of options that are able to reduce the metal line resistance at tight metal pitches, and in the process reduce the resistance/capacitance (RC) increase of future interconnects using direct metal patterning.

For the first time, high aspect ratio (AR=6) processing of ruthenium (Ru) in a semi-damascene fashion has been experimentally shown to result in around a 40% resistance reduction without sacrificing area. Additional simulations confirm the benefits at circuit level in combination with airgaps as dielectrics. A complementary experimental study shows that the reliability of semi-damascene with airgaps is competitive when compared to dual-damascene with low-k dielectrics.

After providing the first experimental demonstration of a functional two-metal-level semi-damascene module at 18nm metal pitch, AR=3, with fully self-aligned vias at VLSI 2022, imec proposes to extend this integration scheme to further reduce the line resistance of the Ru interconnects, while keeping the same footprint.

According to imec, this can be achieved by high-AR processing of the Ru lines using an advanced subtractive metal etch process.

Commenting Zsolt Tokei, Program Director of Nano-interconnects, said, “We measured a significant line resistance reduction of about 40% on Ru lines with AR=6 compared to lines with conventional AR=3. In addition, we showed the benefits at circuit level of implementing high-AR semi-damascene lines with airgaps.”

In another benchmark study, imec demonstrated that the semi-damascene flow with airgaps is reliable with more than 10 years lifetime.

“With no less than 10 oral presentations at this year’s IITC, addressing the main challenges in interconnect scaling, imec has a proven path to push the interconnect roadmap for the coming ten years,” concluded Tokei. “The papers cover advances in semi-damascene integration as a promising interconnect scheme for future logic nodes, memory technologies and highlight progress in middle-of-line (MOL) metallization schemes, dielectrics, alternative metals exploration, and reliability.”

Image: A cross-section TEMs of Ru lines with 18nm metal pitch: (left) AR 3, (right) AR 6. The TEMs demonstrate a nearly vertical profile of the Ru lines and scalability of the current scheme towards higher ARs