Rapidus said that it would be collaborating with Siemens to jointly develop a process design kit based on the Calibre platform, the verification solution that provides highly accurate and efficient physical verification, manufacturing optimisation and reliability assessment from design through to fabrication, while continuing to further its design and verification ecosystem.
This collaboration supports the manufacturing for design (MFD) concept advocated by Rapidus to achieve high yield and short turnaround time from the early stages of manufacturing.
In addition, Rapidus and Siemens EDA will build a reference flow that holistically supports design, verification and manufacturing from front-end to back-end. This reference flow will provide a smooth development environment for Rapidus’ Rapid and Unified Manufacturing Service (RUMS).
“Our work with Rapidus signifies the deep integration of Siemens’ EDA technology into a new manufacturing base. Through the creation of a reference flow utilising products such as Calibre and Solido, we will jointly build a future of semiconductor manufacturing that excels in reliability, speed, scalability and safety,” said Mike Ellow, CEO of Siemens EDA, Siemens Digital Industries Software.
Rapidus is working to integrate the entire foundry process from design to manufacturing. With the secure management of design data, ensuring manufacturing traceability and reducing information leakage risks through collaboration with EDA providers, Rapidus is aiming to strengthen its supply chain reliability.
“Rapidus is dedicated to advancing the co-optimisation of manufacturing and design and is committed to providing a design environment that dramatically speeds up the realisation of customer needs for next-generation semiconductors. Our collaboration with Siemens will embody this mutual optimisation, for our Design Manufacturing Co-Optimisation (DMCO) concept,” said Dr. Atsuyoshi Koike, CEO of Rapidus. “As a state-of the-art semiconductor foundry, we will dramatically shorten the time to tape-out by achieving MFD for the 2nm gate-all-around process.”
