Rambus tapes out 112G XSR SerDes PHY on 7nm process

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Rambus has announced the tapeout of its 112G XSR SerDes PHY on a leading-edge 7nm process node optimised for PPA to support data centre, networking, HPC, AI and ML applications.

As the adoption of chiplet architectures accelerates for networking and compute applications, the Rambus 112G XSR SerDes PHY represents the latest advancement in high-speed signalling technology for die-to-die (D2D) and die-to-optical engine (D2OE) connections.

Today zettabytes of data are being generated constantly by a wide range of devices including IoT endpoints such as vehicles, wearables, smartphones and appliances. AI and ML add new workloads and new data streams from the data centre to the edge, driving new architectures to move data. These new architectures, combined with the trend toward chip disaggregation and the industry’s transition to 400Gb and 800Gb Ethernet, will require new, faster interconnect solutions.

"As semiconductor markets turn towards chiplets to enable their high-performance products, chip-to-chip interconnects will be critical for maintaining high speed and signal integrity across variable physical distances," said Shane Rau, research vice president, computing semiconductors at IDC. "SerDes PHYs at advanced process nodes, like the 7nm 112G XSR, enable that speed and signal integrity."

“Our 112G XSR SerDes PHY is implemented in the leading-edge 7nm process technology, providing chip and system architects the most advanced platform for their designs,” said Hemant Dhulla, vice president and general manager of IP cores at Rambus. “We are excited to continue our tradition of delivering leading-edge IP solutions that address the systems design challenges of the most demanding applications in networking, HPC and AI.”