According to Cadence the IP delivers the power, performance and area (PPA) efficiency required to build high-port density networking products for next-generation cloud-scale and telco datacentres.
Cadence has been working closely with early adopter customers, who have expressed strong interest in this technology and is now ready to engage broadly with customers to enable their next-generation high-performance computing (HPC) ASICs, machine learning accelerators, and switch fabric SoCs.
• Unique firmware-controlled adaptive power design provides optimal power and performance trade=offs and more efficient system designs based on platform requirements
• DSP-based architecture provides superior data recovery for lossy and noisy channels
• Extended reach capability enables customers to use lower cost PCBs and achieve greater flexibility in PCB and system design
• Multi-rate support, including 112/56Gbps PAM-4 (four-level pulse amplitude modulation) and 56/28/10Gbps NRZ (non-return-to-zero) data rate, provides backward compatibility with legacy equipment operating at lower speeds
• Fully autonomous start-up and adaptation, as well as an integrated BIST (built-in self-test) capable of producing and checking PRBS (pseudo random binary sequence), are supported to enhance IP ease of use,
“The 112G SerDes is a new and critical enabling technology that allows the industry to build out the next-generation 100G, 400G and 800G Ethernet cloud infrastructure more rapidly and cost effectively,” said Lip-Bu Tan, chief executive officer of Cadence. “Our silicon-proven 112G long-reach multi-rate SerDes IP places Cadence at the forefront of high-performance computing system design enablement. By enabling 100Gb/sec per lane, Cadence’s solution reduces the lane count, heat dissipation and cost required to build the next generation of hyperscale infrastructure.”