This SOT-MRAM array chip is intended to showcase an innovative computing in memory architecture with a power consumption of just one percent of a spin-transfer torque magnetic random-access memory (STT-MRAM) product.
The collaborative efforts of these two companies have resulted in a research paper on this microelectronic component, which was jointly presented at the 2023 IEEE International Electron Devices Meeting (IEDM 2023), underscoring the cutting-edge nature of their findings and their pivotal role in advancing next-generation memory technologies.
Dr. Shih-Chieh Chang, General Director of Electronic and Optoelectronic System Research Laboratories at ITRI, highlighted the collaborative achievements of both organisations.
“Following the co-authored papers presented at the Symposium on VLSI Technology and Circuits last year, we have further co-developed a SOT-MRAM unit cell,” said Chang. “This unit cell achieves simultaneous low power consumption and high-speed operation, reaching speeds as rapid as 10 nanoseconds. And its overall computing performance can be further enhanced when integrated with computing in memory circuit design. Looking ahead, this technology holds the potential for applications in high-performance computing (HPC), artificial intelligence (AI), automotive chips, and more.”
The advent of AI, 5G, and AIoT has created a significant demand for rapid processing, necessitating new memory solutions that are characterised by enhanced speed, stability, and energy efficiency.
