A new 7-bit 150 GSa/s Digital-to-Analogue Converter (DAC), fabricated in a 5nm FinFET CMOS process, has been able to achieve data rates of up to 300 Gb/s using PAM-4 modulation and has been designed to address the growing demand for faster data centre links.
The demand for higher data transfer rates in data centres continues to increase as data-intensive applications become more prevalent and to handle the vast amounts of data flowing through these centres, wireline communication systems rely on analogue-to-digital converters (ADCs) and digital-to-analogue converters (DACs) to convert analogue signals to digital data and back, allowing the use of sophisticated signal processing supporting transmission over physical links.
However, as data volumes have continued to rise, ADCs and DACs are having to convert data at increasingly higher speeds to ensure efficiency.
Ultra-fast ADCs and DACs are therefore essential to ensure data flow in next-generation wireline systems, but conventional architectures often fall short, resulting in signal degradation and power inefficiencies.
At the same time, power efficiency is becoming increasingly important, as the amount of interconnect deployed inside large-scale data centre infrastructures grows at an even faster pace than the amount of compute.
Imec’s DAC addresses these challenges by achieving a high-speed 150 GSa/s sample rate, capable of generating data rates up to 300 Gb/s using PAM-4. With increasing data rates, PAM-4 has emerged as the preferred modulation scheme in data centres, as it enables faster data transfer without requiring more bandwidth.
“This 7-bit DAC is designed for next-generation data centre links, targeting data rates above 200 Gb/s and ultimately reaching 400 Gb/s per lane. In order to efficiently manage these speeds, the necessary signal processing is implemented in advanced CMOS nodes such as 5nm FinFET. Consequently, the DAC must also be realised within the same technology node,” said Peter Ossieur, program manager for high-speed transceivers at imec.
To optimise power efficiency, imec has drastically reduced the number of unit cells from 127 to 34. This has minimised switching activity, effectively lowering power consumption (to 621 mW at 0.9V and 0.96V supplies) without compromising speed. This reduction also decreases parasitic effects, enabling more accurate signal conversion at higher data rates.
“Looking ahead, the team aims to address the growing demand for even faster data links by targeting the next generation of ADCs and DACs based on 3nm CMOS technology,” Ossieur added. He continued, “The focus is on doubling the sampling rate to 300GSa/s and pushing bandwidth beyond 100GHz. To achieve such speed imec will draw on its expertise in analogue design, and now also addresses the design of ultra-low-jitter clock generation circuitry targeting femtosecond-level accuracies.”
