Imec enables small, low-noise, low-power neural interfaces

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At the IEEE VLSI Symposium on Technology and Circuits, imec has presented a scalable neural readout microchip that features one of the world’s smallest recording channels for the simultaneous acquisition of local field potentials and action potentials in neurophysiology experiments.

The chip is based on an AC-coupled 1st order delta-delta-sigma (Δ-ΔΣ) architecture that enables the conversion to the digital domain very close to the weak analogue signal source. According to imec, this ultra-small direct-digitisation channel holds the promise for even higher density neural recording tools than those existing today.

Low power and small area become crucial IC design challenges for the development of high-channel-count neural interfaces. Recently, several new readouts architectures have been investigated to meet these demands, while still trying to maintain good performance in other metrics such as noise, electrode DC offset cancellation and input range.

A trade-off between all these metrics, however, is not easy to achieve. Direct-digitisation front-ends that convert the signals from the analogue to the digital domain close to the signal source, have shown great potential. But while they dramatically reduce the area, they can still consume high power or exhibit limited bandwidth and/or electrode DC offset cancellation.

Imec has now presented a digitally-intensive neural recording IC that achieves noise, power and area performances comparable to or better than the current state-of-the-art Neuropixels designs, while at the same time increasing the dynamic range and electrode DC offset tolerance via an AC-coupled Δ-ΔΣ modulator.

“Our design succeeded in combining AC coupling and direct digitisation to achieve rail-to-rail DC offset cancellation and a higher input range (43 mVpp) than other AC-coupled designs. This is essential to prevent saturation of the recording channels and tolerate possible movement/stimulation artifacts. The AC-coupled input stage further reduces the power consumption (total per channel of 8.34 μW) since only AC signals are digitised,” explained Carolina Mora Lopez, team leader of the Circuits for Neural Interfaces Team, imec.

This specific Δ-ΔΣ architecture enables the implementation of a large part of the functionality – e.g. the anti-aliasing filter – in the digital domain. As a consequence, it is now possible to significantly shrink the total channel area (0.005 mm2) and improve the signal quality by leveraging the advantages of a highly-scaled technology node (22nm FD-SOI).

“This scalable digitally-intensive design ensures a small footprint and low-power IC with good performance for the concurrent acquisition of neural signals. It’s opening the way towards even smaller probes with higher electrode densities that would drive neuroscientific research forward,” concluded Carolina Mora Lopez.

Photo shows the 128-channel fabricated readout IC