InferX, Flex Logix’s second IP offering to date, can be used by device manufacturers and systems companies that want the performance of a DSP-FPGA or a AI-GPU in their SoC but at, what the company says, is a fraction of the cost and power. The company’s first IP product line – the EFLX eFPGA - has already been proven in dozens of chips with many more in design from 180nm to 7nm with 5nm in development.
“By integrating InferX into an SoC, customers not only maintain the performance and programmability of an FPGA or GPU, but they also benefit from much lower power consumption and cost,” explained Geoff Tate, Founder and CEO of Flex Logix. “This is a significant advantage to systems customers that are designing their own ASICs, as well as chip companies that have traditionally had the DSP-FPGA or AI-GPU sitting next to their chip and can now integrate it to get more revenue and save their customer power and cost. InferX is 80% hard-wired, but 100% reconfigurable.”
With InferX AI, users can process megapixel images with much more accurate models like Yolov5s6 and Yolov5L6 to detect images at smaller sizes/greater distances than is currently affordable.
InferX DSP is InferX hardware combined with Softlogic for DSP operations, which Flex Logix provides for operations such as FFT that is on-the-fly switchable between sizes (1K to 4K to 2K); FIR filters of any number of taps; Complex Matrix Inversions 16x16 or 32x32 or other size, among many more.
InferX DSP streams Gigasamples/second, can run multiple DSP operations, and DSP operations can be chained - DSP is done on Real/Complex INT16 with 32-bit accumulation for very high accuracy.
According to Flex Logix, it also enables users to integrate DSP performance that is as fast or faster than the leading FPGA at a tenth of the cost and power, while keeping the ability to reconfigure almost instantly. One example is InferX DSP with <50 square millimetres of silicon in N5 can do Complex INT16 FFTs at 68 Gigasamples/second and switch instantly between FFT sizes from 256 to 8K points – which is significantly faster than the best FPGA currently available and at a fraction of the cost, power and size.
InferX AI is InferX hardware combined with the Inference Compiler for AI Inference. Inference Compiler takes in a customer’s neural network model in Pytorch, Onnx or TFLite formats, quantizes the model with high accuracy, compiles the graph for high utilisation and generates the run time code that executes on the InferX hardware. A simple, easy-to-use API is provided to control the InferX IP.
InferX AI has been optimised for megapixel batch=1 operations, and the inference compiler is available for evaluation. As an example, with about 15 square millimetres of silicon in N7, InferX AI can run Yolov5s at 175 Inferences/second: this is 40% faster than the fastest edge AI module, Orin AGX 60W.
InferX technology is proven in 16nm and production qualified and will be available in the most popular FinFet nodes.
InferX hardware is also scalable. Its building block is a compute tile that can be arrayed for more throughput. For example, a 4 tile array is 4x the performance of a 1 tile array. The InferX array with the performance the customer wants is delivered with an AXI bus interface for easy integration in their SoC.
