This innovation is designed to address the growing complexity and scalability challenges of RISC-V SoC designs at a time when the open-source RISC-V architecture is increasingly being used across embedded applications. While RISC-V offers flexibility and openness, the RTL design process for RISC-V SoCs is created and optimised using internal solutions (through custom scripts) and remains largely manual particularly for multicore processors and large-scale architectures.
Despite internal scripting and tools, current front-end integration processes face structural inefficiencies such as a lack of design reusability as designs are typically built for specific configurations and lack portability across projects.
Building a complex SoC design project typically involves several key steps: selecting and configuring IPs, interconnecting them, generating the necessary design files for implementation and verification flows, and completing the validation phase.
This entire process is repeated for each new project, and this results in time loss and inefficiency as teams must recreate design integration from scratch.
From IP selection and configuration to connection and file generation, the process remains predominantly manual. Iterating over large RISC-V SoCs is time-consuming and error-prone.
For the same IP core, managing the gap between internal and updated open-source IPs is a challenging process. Differences between open-source RISC-V IPs (e.g. GitHub-based) and customised internal versions require attention and continuous updates.
Modifications to one affect modifications to the other, and teams waste time and energy coordinating all together.
Defacto’s SoC Compiler allows users to quickly explore and generate different SoC configurations - from RTL to design collaterals - based on user specifications, with minimal manual parametrization and intervention.
The company’s new software includes, in-depth RTL linting checks by covering VHDL, Verilog and System Verilog languages. Also, structural checks such as connectivity, clock tree and interfaces checks etc.
The Defacto software delivers a comprehensive set of features designed to optimise SoC integration pre synthesis and includes an optimised and up-to-date library of configurable RISC-V IP cores, along with the ability for users to integrate their own custom IPs.
Using Python or Tcl APIs, designers can leverage a variety of SoC design templates to accelerate development, while built-in checking capabilities ensure quality through linting checks for IP cores and coherency checks between multiple design views. The tool is fully compatible all RTL languages Verilog, VHDL, and SystemVerilog, and offers extensive customisation options to adapt to diverse project requirements.
In addition, the RTL restructuring features such as Feedthrough management enable designers to optimise Power, Performance, and Area (PPA). They help adapt the design to fit with physical requirements by refining structures such as removing long loops, loopbacks, and redundant ports. These enhancements support aggressive die size reduction and significantly improve the reusability of designs and IPs across projects.
The tool also facilitates the integration of design changes, speeding up the iteration process and optimizing coordination between teams.
With Defacto’s SoC Compiler, RISC-V design configuration has been simplified and is faster than using manual methods.
Engineering teams can efficiently generate and manage RISC-V-based SoC designs, resulting in faster design cycles and reduced turnaround time and they can dedicate more attention to debugging, optimisations, and high-value design tasks, while also benefiting from improved reusability of IPs and architectures across projects.
This approach is seen as aligning better with the growing demand for scalable and automated design methodologies as RISC-V continues to expand its footprint in high-performance embedded applications.
