Imperas unifies RISC-V verification ecosystem with RVVI

2 min read

Imperas Software, a developer of RISC-V simulation solutions, has announced the official 1.0 release of the RVVI (RISC-V Verification Interface) as a foundation for the new RISC-V verification ecosystem.

The open standard ISA (Instruction Set Architecture) of RISC-V has generated interest in optimised processors across many different market segments and application areas.

Previously, SoC developers have been constrained by only being able to consider a few limited mainstream IP cores. The design freedom of RISC-V has therefore generated significant interest for innovation.

This design freedom is also migrating the verification responsibility from a few IP providers to all adopters that choose to exploit these new design freedoms associated with RISC-V.

Successful processor adoption has previously focused on software (such as development tools, compilers, and operating systems), and hardware (EDA tools for RTL simulation, gate level synthesis, and physical layout) and while all ISA’s have many unique and special features, these dual ecosystems of hardware and software have been able to support them all. However, since previous processor IP cores were all single sourced, the verification task tended to be performed in house with techniques that were closely guarded as trade secrets.

In addition, since ‘known-good’ processor IP was the base assumption for all SoC verification flows, the processor IP cores were not tested by the SoC adopters. Now with RISC-V, as an open standard ISA, any developer can explore the full range of the design features offered by the ISA specification. This means that all adopters that choose to extend, modify or build a custom processor core will also need to address the design verification (DV) requirements.

Imperas recently announced the ImperasDV solution with a combination of a quality reference model, test suites and verification methodology to address the full spectrum of RISC-V implementations.

The RTL of the device under test (DUT) is typically set-up with a test bench to control and monitor the operational analysis during the verification process. The test bench needs to support all the features of the core, including the specialist DV tasks for test and analysis with debug operations. As the test bench interfaces to the processor RTL (DUT), test generators, reference model, verification IP, and the EDA tools for RTL simulation, any errors or admissions have a significant impact on the quality of the testing and could allow errors to escape unnoticed into late stages of the design, silicon prototypes, or even production devices.

While a custom test bench could be created for any target DUT, this approach limits the options for reuse and leverage other components that could save time and effort.

The new RVVI open standard and methodology, is based on an open specification and can be adapted to any configuration permitted within the RISC-V specifications.

In adopting the RVVI standard, developers will be able to leverage all the common components off the shelf and explore additional options with 3rd party Verification IP. In addition, since many projects evolve into further enhancements for successor designs, the investment in the verification infrastructure can be reused for both future core projects and ongoing regression frameworks.

RVVI technical summary

New open standard RVVI (RISC-V Verification Interface) provides:

  • Seamless integration between RTL, reference model and testbench
  • Close-coupled integration for instruction accurate lock-step-and-compare
  • Supports multi-hart, superscalar and out-of-order CPU pipelines
  • Fully compliant with the standards for UVM
  • SystemVerilog integration compatible with the tools and environments offered by Cadence, Siemens EDA, Synopsys, and the Metrics cloud-based tools.
  • The new RVVI (RISC-V Verification Interface) is an open standard developed by Imperas with guidance and support from lead customers and users, is available now, and is being adopted by the RISC-V test and verification community.

“We are at the epicentre of the biggest migration of verification responsibility in the history of processor IP and EDA tools,” said Simon Davidmann, CEO at Imperas Software. “Now every SoC design team can embrace the processor design flexibility of RISC-V for optimised domain specific solutions – but this marks the end of the ‘one-size-fits-all’ era of processor IP. Expanding the scope of the established SoC verification flows to accommodate the additional complexity of RISC-V processor DV is defining the new verification ecosystem, which is unique for the adopters of the RISC-V ISA.”