Codasip joins Intel Pathfinder for RISC-V programme

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Codasip, a specialist in processor design automation and RISC-V processor IP, is to make its 32-bit L31 core available through the Professional Edition of the Intel Pathfinder for RISC-V programme.

By joining the programme, Codasip is making its embedded RISC-V technology more accessible for prototyping, production design or research purposes using Intel FPGAs.

Particularly in the early stages of the SoC development cycle, it is beneficial to undertake architectural exploration and to explore different configurations and combinations of IP. The Intel Pathfinder provides a common environment for accessing RISC-V and peripheral IP for its FPGA boards.

“FPGAs are an essential part of the electronics industry both in prototyping and production” says Rupert Baines, Chief Marketing Officer Codasip, “We welcome Intel’s investment in this programme.  Its demonstrable commitment to RISC-V will benefit the entire RISC-V ecosystem.”

“The rapid emergence of RISC-V is opening up new avenues for building products and solutions. We are striving to galvanize the RISC-V ecosystem around a shared vision to accelerate adoption.  Towards that goal, we are excited to see Codasip enable their processor IP for Intel Pathfinder for RISC-V,” said Vijay Krishnan, General Manager, RISC-V Ventures from Intel.

It is also increasingly important to start the development of software early in the design cycle. This programme includes a unified IDE and software stack including software toolchains and commonly used operating systems providing the essentials for embedded software developers.

As a result of the agreement, Intel FPGA boards and the Intel software stack can now be combined with Codasip bitmap file for the L31 RISC-V core. This benefits developers in applications such as Internet of Things (IoT) and edge AI.

The Codasip L31 is a 32-bit embedded RISC-V core supporting the RV32IMCB instruction set. It has a 3-stage pipeline and a range of configuration options including caches and tightly coupled memories.