CEVA joins Intel Pathfinder for RISC-V programme

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CEVA, a licensor of wireless connectivity and smart sensing technologies, is to make its CEVA-BX1 and CEVA-BX2 Audio DSPs and audio front-end software stack available for commercial developers through the Intel Pathfinder for RISC-V* ecosystem.

A Strategic Member of RISC-V International, CEVA is making its audio DSPs and software stack accessible for prototyping and production design through the Intel FPGA based pre-silicon development platform.

Commenting Moshe Sheier, Vice President of Marketing at CEVA, said, “DSP is an essential technology for processing complex audio and voice workloads and this initiative makes it easier for the RISC-V ecosystem to research, evaluate and eventually productize SoCs incorporating our best-in-class IPs.”

“The availability of CEVA’s Audio DSPs and software IP for the Intel Pathfinder for RISC-V programme is another step in our commitment towards simplifying and accelerating the development of RISC-V platforms,” explained Vijay Krishnan, General Manager, RISC-V Ventures from Intel. “Complementary IP plays an important role in the RISC-V ecosystem and we’re pleased to partner with an industry leader like CEVA to broaden the IP offerings available to our users.”

The CEVA-BX1 processor combines efficient DSP compute capability with high-level programming and compact code size requirements of embedded applications targeting hearables, wearables and other low power smart audio use cases.

Using an 11-stage pipeline and 4-way VLIW micro-architecture, it offers parallel processing with a Single Instruction Multiple Data (SIMD) ISA, widely used in neural networks inference, noise reduction and echo cancellation, as well as high accuracy sensor fusion algorithms.

The CEVA-BX2 is targeted at high performance audio devices and uses quad 32X32-bit MACs and octal 16X16-bit MACs, with enhanced capability to support 16×8-bit and 8×8-bit MAC operations. Its 11-stage pipeline and 5-way VLIW micro-architecture, support parallel processing with dual scalar compute engines, load/store and program control.

The CEVA-BX Instruction Set Architecture (ISA) incorporates support for Single Instruction Multiple Data (SIMD) as well as optional floating-point units for high accuracy algorithms. The CEVA-BX is accompanied by a comprehensive software development tool chain, including an advanced LLVM compiler, eclipse-based debugger, DSP and neural network compute libraries, neural network frameworks support and Real Time Operating Systems (RTOS).