Codasip introduces latest RISC-V core for power-efficient applications

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Codasip has introduced a new low-power embedded processor core, and the next generation of processor design automation toolset Codasip Studio.

Credit: Codasip

The Codasip L110 has been developed to deliver ‘best-in-class’ performance for power-sensitive applications. In addition, customers will be able to add their unique customisations for application-specific PPA (Power, Performance, and Area) improvements.

A new level of customisation in Codasip Studio Fusion, called Bounded Customisation, lets customers achieve a fast time to market for high-quality, fully verified RISC-V cores. The core can be extended with new instructions without risk because the functionality of the baseline core is guaranteed. A new verification framework substantially simplifies the verification of custom instructions.

"Customisation allows designers to introduce new instructions specific to their software workload and significantly improve PPA,” commented Brett Cline, chief commercial officer at Codasip. “Our new core offers best-in-class performance for small-area and low-power applications accompanied by new possibilities for easy and quick customisation with no risk to the core functionality."

According to Codasip, the L110 can deliver up to 50% improvements in performance per watt and 20% smaller code size compared to similar cores in the market.

The core offers extensive configurability, allowing different area/performance trade-off levels, and support for standard RISC V code-size extensions. In addition, the L110 is fully customisable allowing designers to extend the processor to achieve PPA improvements to differentiate their products.

Designed by the Codasip team using Codasip Studio Fusion, the L110 is suitable for small-area, low-power applications, such as state machine replacements, sensor controllers, and IoT edge.

Codasip Studio has, over the years, been the toolset to generate both the RTL and the software development tools from a single processor model. Codasip Studio Fusion improves this fundamental capability and adds a segmentation layer. Customers can configure the core from set options, create custom instructions within set bounds, or design freely. The tools automatically generate an SDK (Software Development Toolkit) including a compiler, simulation models, debugger, and profiler, and an HDK (Hardware Development Kit) including RTL (Register Transfer Level), a verification framework, and more.

The latest version also introduces more design automation to make processor design even easier and faster. New design constructs allow for fusing the processor's architectural and microarchitectural description, while the toolset can also automatically convert declarative descriptions of common processor aspects into low-level logic.

The benefits of the Codasip Studio Fusion toolset are reflected in the new L110 core, which can be used as a pre-verified starting point to achieve the right level of customisation. For customers in need of a starting point with higher performance, Codasip can offer other options such as the 64-bit RISC-V application core A730.