This new generative design migration flow, jointly developed by Cadence and TSMC, is able to provide a simplified and automated approach to migrate custom and analogue IC designs among TSMC’s process technologies.
According to customers already using the flow, they have been able to successfully reduce migration times by 2.5X when compared with manual migration.
The Virtuoso Design Platform automatically migrates schematic cells, parameters, pins and wiring from one TSMC process node to another. The Virtuoso ADE Product Suite’s simulation and circuit optimisation environment then tunes and optimises the new schematic to ensure the design achieves all required specifications and measurements.
Cadence and TSMC customers can then automatically recognise and extract groups of devices in an existing layout and apply them to similar groups in the new layout, thanks to the Virtuoso Layout Suite’s generative design technology using templates, TSMC’s analogue-mapping and routing technologies in the Virtuoso Design Platform.
“As application requirements grow, many TSMC customers are looking to migrate legacy IC designs to our more advanced nodes, such as N3E and N2, to take full advantage of higher performance and lower power benefits of the latest TSMC advanced technologies,” explained Dan Kochpatcharin, head of the Design Infrastructure Management Division at TSMC. “Our ongoing collaboration with Cadence has resulted in enhanced PDKs and methodologies that simplify and accelerate the design migration process, ultimately speeding time to market.”
“Through this latest collaboration, our joint customers benefit from our advanced technologies that make custom/analogue migration simpler and far less time-consuming,” said Tom Beckley, senior vice president and general manager in the Custom IC, IC Packaging, PCB and System Analysis Group. “Our Virtuoso Design Platform’s proven node-to-node generative design migration technology can shave weeks off the time required to migrate a complex IC design between nodes, which is critical in the highly competitive chip design market.”
