The solution is said to be fully integrated with TSMC’s Chip-on-Wafer-on-Substrate (CoWoS) advanced packaging technology, which has helped to unlock ‘breakthrough’ bandwidth density and scalability for next-generation chiplet architectures.
This announcement builds on the recent release of the Alphawave Semi AI Platform which supports the development of disaggregated SoCs and scale-up infrastructure for hyperscale AI and HPC workloads.
With this tape-out, Alphawave Semi is now one of the industry’s first companies to enable UCIe connectivity on 2nm nanosheet technology, marking a major step forward for the open chiplet ecosystem.
“We’re proud to lead the industry into the N2 era with the first UCIe IP on this advanced node,” said Mohit Gupta, Senior VP & GM, Custom Silicon & IP, Alphawave Semi. “Our 36G subsystem validates a new class of high-density, power-efficient chiplet connectivity and paves the way for 64G UCIe and beyond – which is critical for AI and high-radix networking applications.”
Alphawave Semi’s UCIe IP subsystem delivers 36G performance with 11.8 Tbps/mm bandwidth density, ultra-low power and latency, and has advanced features like live per-lane health monitoring and comprehensive testability. It’s compliant with the UCIe 2.0 standard and supports multi protocols, such as PCIe, CXL, AXI, and CHI using Alphawave Semi’s highly configurable and efficient Streaming Protocol D2D Controller.
Alphawave Semi is working with other companies, within the broader ecosystem, to leverage D2D-based open chiplet interoperability to drive a broader AI connectivity platform for the industry. The company’s UCIe IP on the TSMC N2 process affirms its position as one of the leading enablers of scalable, open chiplet ecosystems.
“Our latest collaboration with Alphawave Semi underscores our shared commitment to driving advancements in high-performance computing through design solutions that fully leverage the performance and energy-efficiency advantages of TSMC’s advanced process and packaging technologies,” commented Lipen Yuan, Senior Director of Advanced Technology Business Development at TSMC. “This milestone illustrates how close collaboration with our Open Innovation Platform (OIP) partners can enable the quick delivery of advanced interface IP and custom silicon solutions to meet the increasing demands of AI and cloud infrastructure.”
