Engineering publications brought to you by Mark Allen

ASIC & SoC

'Chip Builder' lets designers visualise ASIC solutions

UltraSoC and Imperas combine to enhance multicore development and debug

Renesas and Magna develop 3D surround view system

Measuring battery life

A strategy bearing fruit

Chip from Vayyar provides a high resolution, mobile and cost-effective 3D imaging solution

Cadence prototypes first IP interface in silicon for preliminary version of DDR5 standard being developed in JEDEC

UltraSoC selected by Andes for RISC-V development with trace and debug

The dangers of speculation

First integrated FPGA-in-the-loop workflow for PolarFire and SmartFusion2 FPGA development boards

Tackling congestion on programmable devices

Enabling the adaptable world