This open industry standard defines interconnect between chiplets within a package, enabling an open chiplet ecosystem and facilitating the development of advanced 2.5D/3D devices.
As a supplier high-performance memory ICs, Winbond has established itself as a supplier of known good die (KGD) which is needed to assure end-of-line yield in 2.5D/3D assembly and to deliver improvements in performance, power efficiency, and miniaturisation, that are being demanded by the explosion of technologies such as 5G, Automotive , and Artificial Intelligence (AI).
By joining the UCIe Consortium, Winbond will be able to support interconnect standardisation that simplifies system-on-chip (SoC) design and eases 2.5D/3D back-end-of-line (BEOL) assembly. The UCIe 1.0 specification provides a complete standardised die-to-die interconnect with a high-bandwidth memory interface, facilitating SoC-to-memory interconnection for low latency, low power, and high performance.
Ultimately, standardisation will support market growth in advanced multichip engines by accelerating the introduction of higher-performing products that deliver increased value for device makers and end users.
Winbond’s 3D CUBE as a Service (3DCaaS) platform gives customers a one-stop shopping service. It includes 3D TSV DRAM (aka CUBE) KGD memory dies and 2.5D/3D BEOL with CoW/WoW optimised for multichip devices, in addition to a consulting service. Winbond said that by joining the UCIe Consortium it is now positioned to deliver standardised 3D DRAM and 2.5D/3D BEOL services to customers.
“The UCIe specification will enable 2.5D/3D chip technology to realise its full potential in AI applications from the cloud to the edge,” said Hsiang-Yun Fan, DRAM Vice President of Winbond. “This technology has a major role in continuing to raise performance as well as ensuring the affordability of cutting-edge digital services.”
“We’re excited to welcome Winbond to the UCIe Consortium,” said Dr Debendra Das Sharma, Chairman UCIe Consortium. “As a global supplier of performance memory solutions with expertise in 3D DRAM, we look forward to their contributions to further developing the UCIe chiplet ecosystem.”
