According to Synopsys, designers will benefit from a low-latency, high-bandwidth die-to-die connectivity offering that is able to address the increased workload and faster data movement demands of high-performance computing, artificial intelligence (AI) and networking SoCs.
The DesignWare Die-to-Die Controller and PHY IP are part of the Synopsys multi-die solution, consisting of HBM IP and 3DIC Compiler, accelerating SoC designs requiring advanced packaging.
The DesignWare Die-to-Die Controller provides error recovery mechanisms such as optional forward-error correction and cyclic redundancy check for higher data integrity and link reliability. The DesignWare Die-to-Die controller's flexible configuration supporting the AMBA CXS and AXI protocols allows coherent and non-coherent data communication for easy integration into Arm-based and other high-performance SoCs. The DesignWare Die-to-Die Controller with support for up to 1.8Tb/s PHY bandwidth addresses high-performance computing demands of SoCs requiring robust die-to-die connectivity.
"The trend of die splitting and disaggregation require ultra- and extra-short reach links to enable inter-die connectivity with high data rates," said John Koeter, senior vice president of marketing and strategy for IP at Synopsys. "Our complete DesignWare Die-to-Die IP solution offers ultra-low-latency controller and high-performance PHYs that have been adopted by multiple customers, allowing designers to integrate high-quality IP in their multi-die SoCs with confidence while minimizing integration risk."
Synopsys' broad DesignWare IP portfolio includes logic libraries, embedded memories, IOs, PVT monitors, embedded test, analogue IP, interface IP, security IP, embedded processors and subsystems.
To accelerate prototyping, software development and integration of IP into SoCs, Synopsys' IP Accelerated initiative also offers IP prototyping kits, IP software development kits and IP subsystems.