According to Siemens, the solution enables integrated circuit (IC), place-and-route (P&R) and full-custom design teams to improve productivity, raise design quality and reduce time to market. It does this by automatically implementing ‘Calibre correct-by-construction’ design layout modifications much earlier in the IC design and verification process.
The latest in a series of ‘shift left’ tools for Siemens’ Calibre nmPlatform for IC physical verification, Calibre DesignEnhancer empowers custom and digital design teams to enhance physical verification readiness by quickly and accurately optimising their designs to reduce or eliminate voltage (IR) drop and electromigration (EM) issues.
By supporting automated layout optimisation during the IC design and implementation stages, the tool helps customers deliver “DRC-clean” designs to tapeout faster while improving design manufacturability and circuit reliability.
Before conducting physical verification on an IC design, engineers have traditionally relied on third-party P&R tools to incorporate design for manufacturing (DFM) optimisations, often requiring multiple time-consuming runs before converging on a “DRC-clean” solution. Using the Calibre DesignEnhancer tool, however, design teams can now significantly shorten turnaround time and reduce EM/IR issues while preparing a layout for physical verification.
The Calibre DesignEnhancer tool currently provides three use models:
Via modification automatically analyses layouts and inserts up to 1 million+ Calibre-clean correct-by-construction vias to reduce the impact of via resistance on EM/IR and reliability. Because these modifications are based on a thorough understanding of the layout and signoff design rules, via insertion can help customers meet their power goals without impacting performance or area metrics.
Power/ground enhancement automatically analyses layouts and inserts Calibre nmDRC-clean vias and interconnects in open tracks to create parallel runs that can lower resistance on power/ground structures and reduce IR and EM issues associated with the power grid. Customers using the Calibre DesignEnhancer tool have achieved up to 90 percent reductions in IR drop issues.
Filler cell insertion is able to optimise the insertion of decoupling capacitor (DCAP) and filler cells required for physical verification readiness. It replaces traditional P&R filler cell insertion processes, which helps to provide better quality of results and up to 10X faster runtimes.
“In today’s challenging IC design environment, engineering teams working at advanced nodes are struggling to optimise layouts for manufacturability and performance within the given area and project timeline constraints in which they must work,” said Michael White, Senior Director, Physical Verification Product Management, Calibre Design Solutions, Siemens Digital Industries Software. “By using the Calibre DesignEnhancer software, designers can bring Calibre polygonal processing speed and accuracy into play earlier in the design cycle, which can help to avoid late design cycle surprises.”
The Calibre DesignEnhancer solution uses proven technology, engines, and qualified rule decks from Calibre. It can read OASIS, GDS, and LEF/DEF as input files, and output layout modifications in any combination of OASIS, GDS, or incremental DEF files, helping design teams to easily back-annotate Calibre DesignEnhancer software changes to the design database for power and timing analysis using commonly preferred tools for further analysis earlier in the design creation lifecycle.
The tool integrates with all major design and implementation environments using industry interface standards, providing a user-friendly environment that requires minimal training and setup. Calibre DesignEnhancer kits are available now for all leading foundries supporting designs from 130nm to 2nm, depending on the use model and the technology.
