These developments seek to address some of the fundamental challenges facing data centres about how to deal with the rapidly increasing amount of data as AI evolves. Sarcina’s work in photonic package design looks to enable higher data rate, higher bandwidth and lower power interconnects.
Traditional copper interconnects can no longer meet the performance, power and density demands of next generation data centre systems and are inadequate when the signal traveling distance is longer than a few meters, due to excessive insertion loss of a copper cable.
Consequently, system architects are increasingly moving towards optical integration at the package level because it can deliver higher bandwidths, lower latency, greater energy-efficiency, space-saving and longer transmission distances.
According to Larry Zu, CEO at Sarcina Technology, the company’s approach to Co-Packaged Optics removes the long copper trace between the switch and the optical module, replacing it with short, high-integrity connections between ASIC and optics.
“This is made possible because of our unique package design skills, creating novel layout architectures and integration schemes that directly integrate switch ASICs to photonic ICs inside a package. As the recent rise in AI applications puts more and more pressure on data centre systems, the need for this expertise has never been greater.”
Sarcina’s design approach is rooted in four key disciplines: electrical performance, optical alignment, thermal control and mechanical robustness and it packaging solutions are carefully architected to achieve high signal integrity under high data rate of transmission, power integrity simulation; thermal management and mechanical reliability; compact optical integration and long-term system durability.
The company’s design portfolio includes full-package architecture for integrating photonic and electronic components in a single module. These include:
Silicon Photonics Co-Design: Seamless integration of PICs and ASICs with optimized placement, signal routing and thermal dissipation.
Opto-Electronic Interface Engineering: Coordinated electrical and optical layout ensuring clean transitions and minimal loss, verified through high-speed signal integrity simulation across package layers and interfaces.
Multi-Chip Module (MCM) Layout: Architecting packages that bring together ASICs, modulators, drivers, TIAs and passives in the form of bare dice or chiplet, packaged ASICs from various package types and in unified 2.5D or 3D layouts.
Precision Optical Coupling: Developing alignment strategies and mechanical structures that support micron-accuracy fibre and lens placement within package constraints.
“Sarcina's expertise in both high-speed electrical packaging and Co-Packaged Optics with Silicon Photonics chiplets is particularly valuable as the industry shifts toward co-packaged solutions to improve data transmission efficiency and reduce power consumption,” explained Zu. “By seamlessly integrating multiple ASIC dice with optical components, Sarcina addresses challenges facing data centres that traditional semiconductor or optical companies might struggle with. It will be exciting to see how this kind of cross-disciplinary capability can shape next-generation connectivity and computing solutions.”
