According to the researchers, the development should enable high density spin-transfer-torque MRAM (STT-MRAM) arrays to be made on10nm processes and beyond. It is also said to pave the way for high density standalone applications.
STT-MRAMs – seen as an alternative to DRAM – feature a magnetic tunnel junction (MTJ) in which a thin dielectric layer is sandwiched between a magnetic reference layer and a magnetic free layer. The memory is written by switching the magnetisation of the free layer. While STT-MRAMs exhibit non volatility, high speed, low voltage switching and nearly unlimited read/write endurance, significant challenges need to be overcome before they can be commercialised.
Looking to address these challenges, imec’s team has demonstrated a p-MTJ stack with a free layer and reference layer of CoFeB-based multilayer stacks. Created on 300mm silicon wafers, the fabrication process is said to be compatible with standard CMOS back-end-of-line technology.
The researchers say they have also integrated arrays of p-MTJ devices into a 1T1MTJ structure, allowing them to build Mbit arrays of STT-MRAM elements with pitches down to 100nm. This, they contend, proves the technology can be used at the 10nm node and beyond.
“STT-MRAM is a promising memory concept for future technology nodes, but its scalability has always been challenging,” said Gouri Sankar Kar, who coordinates imec’s STT-MRAM activities. “Our demonstration of a high-performance p-MTJ device as small as 8nm, combined with a manufacturable solution for a scalable STT-MRAM array, will open up continued innovations for embedded non-volatile memory applications in the 10nm logic node.”