The main blocks on the SoC are two AI accelerators with 10 TOPS aggregated performance, two Dream Chip Realtime Pixel Processor (RPP) high-performance automotive Image Signal Processors (ISPs), an ARM Cortex-R52 based functional safety processor (Alcatraz), a dual-core ARM Cortex-A65 processor cluster, and an Arteris FlexNoC Network-on-Chip.
The two AI accelerators are a Neural Processing Unit (NPU) from the TU Dresden and a NPU from Cadence (NNA110). The NPU from the TU Dresden is a circuit that consists of a RISC processor with a local programme memory, 768 Processing Elements (PE) with closely coupled memory, and a local DMA controller.
The NNA110 is a Deep Neural Network Accelerator which has been optimised for artificial intelligence (AI) empowered vision, audio, radar/lidar, and fused sensor applications, delivering industry leading performance and power efficiency by taking advantage of sparsity in weights and activations. Together the two AI cores achieve a total of 10 TOPS with INT8 precision.
Dream Chip’s two low-latency 5k line size image signal processors support CMOS sensors up to 19.6 MPixel and perform image processing tasks without impacting the Cortex-A65AE or Cortex-R52 performance. The ISP was developed by Dream Chip according to the ISO26262:2018 standard and is certified up to ASIL-B/-D by TÜV Süd. A 24-bit hard-wired image pipeline with low energy consumption is used. The ISP requires no additional frame buffer which leads to a very low latency of 200µs.
Alcatraz is Dream Chip’s patented safety island subsystem for automotive applications, based on the ARM Cortex-R52 dual-core lock-step processor. The safety island subsystem will be used inside automotive SoCs to supervise application processors and to detect and handle safety violations.
The Application Processor Unit (APU) is based on a Dual-core ARM Cortex-A65AE processor subsystem that is suitable for running an application Operating System (OS), e.g. Linux or QNX.
Dream Chip executed the complete design cycle from architecture to tape-out in this project, including the integration of all internal and external IP (intellectual property blocks and subsystems) and future bring-up/ post-silicon validation as well as the reference board design.
The SoC has 1.8 billion transistors and will be produced in the 22FDX technology of GlobalFoundries in Dresden, Germany, to support the local European semiconductor supply chain for automotive applications. First Samples will be available in Q4/2023.
"Developing this advanced automotive SoC that combines AI performance with functional safety and the newest image signal processing is a major step towards providing OEMs and Tier-1s in Germany with semiconductor solutions on which they can develop modern automotive applications,” said Dr. Jens Benndorf, Managing Director and Co-Founder of Dream Chip Technologies. "Dream Chip shows with this SoC the capability to execute chip design from architecture to tape-out with Dream Chip being the right interface to the foundries in the semiconductor supply chain.”
