CEVA DSP architecture addresses compute requirements of 5G-Advanced

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CEVA, a licensor of wireless connectivity and smart sensing technologies, has announced its 5th generation CEVA-XC DSP architecture.

Said to be its most efficient to date, the CEVA-XC20 is based on a vector multi-threaded massive compute technology that is designed to address next-generation 5G-Advanced workloads across a broad spectrum of use cases, including smartphones, high-end Enhanced Mobile Broadband (eMBB) devices (e.g. Fixed Wireless Access and Industrial Terminals) and a range of cellular infrastructure devices (e.g. base stations, virtualized DU accelerators, and beamforming compute in Massive MIMO radios).

SoC and ASIC designers incorporating the CEVA-XC20 architecture will benefit from its power efficiency when it comes to designing greener processors that are smaller and lower power.

Commenting on the DSP architecture, Dimitris Mavrakis, Senior Research Director at ABI Research, said, “CEVA’s latest DSP architecture raises the bar for performance and power efficiency in 5G-Advanced cellular baseband processing, adopting a unique multi-thread scheme to address the challenging power, performance and area constraints when dealing with complex 5G scenarios.

“The CEVA-XC20 offers a compelling solution to any wireless semiconductor or OEM developing their own 5G-Advanced silicon, and can play a critical role in helping customers to address their sustainability goals in the process.”

The CEVA-XC20 architecture was designed in consultation with leading Tier 1 OEM customers, with the aim of improving mobile network performance and power efficiency.

The CEVA-XC20 looks to address the performance challenges posed by next-generation compute-intense 5G-Advanced by employing a Dynamic Vector Threading (DVT) scheme, which supports hardware multi-threading, which up until now was only found in general purpose CPU architectures. DVT enables optimal sharing of vector resources between different execution units, resulting in an unprecedented vector utilisation efficiency boost.

This technique achieves optimal utilisation of the VLIW architecture and improves core efficiency for common 5G execution kernels, as well as significantly enhancing use cases involving multi-component carriers and multi-execution tasks.

This enables increasing the length of the vector processing units, usually consuming the bulk of the area in vector DSPs, while maintaining and even improving the execution efficiency relative to previous generations.

According to Guy Keshet, Vice President and General Manager of the Mobile Broadband Business Unit at CEVA, “5G-Advanced and beyond promise ever-increasing cellular bandwidth and lower latency, while being greener and more energy efficient. This creates significant challenges for wireless device companies and mobile network operators who need to deliver on this promise.”

The first core based on the CEVA-XC20 architecture is the CEVA-XC22 DSP, supporting two execution threads using the DVT scheme. The CEVA-XC22 offers a 2.5X improvement in efficiency (performance per watt and area) for essential 5G use cases and computation kernels versus its predecessor.

The CEVA-XC22 will also be integrated within CEVA’s holistic baseband platforms, PentaG-RAN for cellular infrastructure and PentaG2-Max for high performance mobile devices, where it will power CEVA’s heterogeneous compute platforms, including both DSPs and compute engine accelerators.

The CEVA-XC22 DSP will be available for general licensing in the second quarter of this year.