Legato has been designed to eliminate the complexity of piecing together point tools for multiple design and verification tasks and, according to Cadence, can result in productivity gains of up to 2X when compared with previous point tool offerings.
Legato automates design steps and lets customers use Cadence’s toolset to deliver products to market faster. The solution includes new patent-pending Super Sweep technology that uses existing simulation databases for multi-corner and Monte Carlo analysis, allowing customers to improve both runtime and simulation throughput.
Legato’s technology capabilities include: a Bitcell design and verification environment, customers can design the bitcell, including variation analysis, without having to leave the design environment; a memory compiler design and verification environment that enables users to design and verify full memory arrays within the Legato Memory Solution and access the Super Sweep technology to improve accuracy and simulation throughput for advanced-node designs and a memory characterization environment, which enables users to create Liberty format models of the memory for system-on-chip (SoC) full-chip analysis.
The tight integration between memory characterization and circuit simulation provides additional accuracy and performance improvements that can’t be achieved by point tools.
“Long simulation times and a high rate of inaccuracy have become bottlenecks in the SoC design cycle schedule,” said Tom Beckley, senior vice president and general manager of the Custom IC & PCB Group at Cadence. “The Legato Memory Solution combines patented technologies interleaved with our existing, proven Virtuoso Liberate MX Memory Characterization Solution, Spectre eXtensive Partitioning Simulator (XPS) and Virtuoso Variation Analysis solutions to improve designer productivity and enable our customers to meet stringent design schedules.”
