Cadence unveils NVMe 1.4 Verification IP for high-performance computing

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Cadence Design Systems is making available the industry’s first Verification IP (VIP) in support of the new NVM Express 1.4 (NVMe) protocol.

The Cadence VIP for NVMe 1.4 is intended to enable designers to verify their storage, data centre and high-performance computing (HPC) system-on-chip (SoC) designs with considerably less effort and a greater assurance that the SoC will meet the protocol standards.

VIP provides customers with a comprehensive verification solution to develop high-quality NVMe host and device controllers quickly, helping reduce overall time to market.

The NVMe 1.4 VIP supports built-in integration with the Cadence VIP for PCI Express (PCIe) 5.0 and includes a complete UVM SystemVerilog API for fast integration and SoC-level test creation. Built using the company’s TripleCheck technology, customers will have access to a verification plan with measurable objectives linked to the specification features and a comprehensive test suite with ready-to-run tests to ensure support for the specification.

“The NVMe 1.4 specification is designed to address the growing needs of enterprise systems that utilize PCIe-based solid-state storage,” said Moshik Rubin, Verification IP Product Management Group Director, System and Verification Group at Cadence. “Cadence is fully dedicated to supporting the latest standard to ensure customers have the tools they need to create differentiated end products. Our release of the first-to-market VIP for NVMe 1.4 is enabling early adopters of the protocol to reduce risk and ensure their designs comply with the specification while achieving the fastest path to IP and SoC verification closure.”

The Cadence VIP with TripleCheck technology is part of the Cadence Verification Suite and is optimised for Xcelium Parallel Logic Simulation, along with supported third-party simulators. The Verification Suite is comprised of best-in-class core engines, verification fabric technologies that support the Cadence Intelligent System Design strategy, enabling SoC design excellence.