Cadence expands Samsung Foundry collaboration

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Cadence Design Systems is expanding its collaboration with Samsung Foundry to accelerate 3D-IC design development.

Targeting next-generation applications like hyperscale computing, 5G, AI, IoT and mobile the collaboration looks to advance multi-die planning and implementation with the delivery of the latest reference flows and corresponding package design kits based on the Cadence Integrity 3D-IC platform – a unified platform that includes system planning, packaging and system-level analysis in a single cockpit.

In addition, the platform supports Samsung’s new 3D CODE standard, a new system description language that simplifies the definition and interoperability of design creation and analysis flows in a unified environment.

Developing advanced package multi-die designs, engineers can come up against design analysis and flow complexities, configuration challenges, and system-level thermal and power integrity issues, all of which extend design turnaround time.

To address these challenges, the unified solution simplifies the multi-die design and implementation process, improving productivity and reducing design turnaround time. The reference flows based on the Integrity 3D-IC platform offer key capabilities, including early analysis for the power delivery network (PDN), thermal and system-level layout versus schematic (LVS) and design rule checking (DRC).

The flows also incorporate the Cadence Allegro X packaging technologies as well as multiphysics system-level analysis tools, Celsius Thermal Solver and Clarity 3D Solver, which provide further productivity benefits.

“Customers creating high-performance designs are looking to make use of the benefits advanced packaging technologies offer, such as lower power, lower yield cost and system performance boosts,” said Sangyun Kim, vice president of the Foundry Design Technology Team at Samsung Electronics. “With the introduction of our 3D CODE technology and Cadence’s comprehensive new flows, we’re providing mutual customers with the next generation chiplet architectures required to achieve multi-die planning and implementation objectives so they can deliver high-quality products to market faster.”

Commenting Vivek Mishra, corporate vice president in the Digital & Signoff Group at Cadence added, “The reference flows based on the Cadence Integrity 3D-IC platform combined with Samsung’s latest technologies provide our customers a unified design environment that simplifies the workflow and reduces multi-die planning and implementation turnaround time when creating complex 3D-IC designs.”